An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems
Issue No.03 - March (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.48872
<p>An improved implementation of clock synchronization of multiprocessor systems in the presence of malicious faults is proposed. The proposed hardware implementation for the reference clock selection has a lower gate complexity, smaller time delay, and greater flexibility than the previously published implementation. The improvement is achieved by replacing the sorter with a counting encoder and comparators and by introducing threshold generation logic with programmable registers. The scheme has a gate complexity of O(n) and a delay of O(log n), where n is the total number of inputs to a particular clock, and is programmable for different values of n and m, the maximum number of faults.</p>
fault-tolerant clock synchronization algorithm; large multiprocessor systems; malicious faults; reference clock selection; lower gate complexity; smaller time delay; sorter; counting encoder; threshold generation logic; programmable registers; gate complexity; fault tolerant computing; multiprocessing systems; synchronisation.
B.-R. Choi, K.H. Park, M. Kim, "An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems", IEEE Transactions on Computers, vol.39, no. 3, pp. 404-407, March 1990, doi:10.1109/12.48872