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W.M. Lin, V.K.P. Kumar, "A Note on the Linear Transformation Method for Systolic Array Design," IEEE Transactions on Computers, vol. 39, no. 3, pp. 393399, March, 1990.  
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@article{ 10.1109/12.48870, author = {W.M. Lin and V.K.P. Kumar}, title = {A Note on the Linear Transformation Method for Systolic Array Design}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {3}, issn = {00189340}, year = {1990}, pages = {393399}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.48870}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A Note on the Linear Transformation Method for Systolic Array Design IS  3 SN  00189340 SP393 EP399 EPD  393399 A1  W.M. Lin, A1  V.K.P. Kumar, PY  1990 KW  linear transformation method; systolic array design; Warshall algorithm; transitive closure; graph; meshconnected array; verification; correctness; I/O bandwidth; processing elements; local storage; cellular arrays; logic arrays; logic design; parallel algorithms. VL  39 JA  IEEE Transactions on Computers ER   
The use of the linear transformation method to systolize the Warshall algorithm for computing the transitive closure of a graph on a meshconnected array (without wraparound connections) is discussed. The technique is extended to design linear systolic arrays. The advantage of this approach is easy verification of correctness, as well as synthesis of a family of arrays with tradeoffs between I/O bandwidth, number of processing elements, and local storage. The technique can be further refined to cope with problems that entail nonconstant dependency vectors.
[1] A. Aho, J. E. Hopcroft, and J. D. Ullman,The Design and Analysis of Computer Algorithms. Reading, MA: AddisonWesley, 1975.
[2] M. Chen, "A design methodology for synthesizing parallel algorithms and architectures,"J. Parallel Distributed Comput., pp. 461491, Dec. 1986.
[3] P. R. Cappello and K. Steiglitz, "Unifying VLSI array design with geometric transformation," inProc. Int. Conf. Parallel Processing, 1983, pp. 448457.
[4] J. A. B. Fortes, K. S. Fu, and B. W. Wah, "Systematic approaches to the design of algorithmically specified systolic arrays," inProc. IEEE Int. Conf. Acoust., Speech, Signal Processing, Mar. 1985, pp. 26 29.
[5] J. A. B. Fortes, "Algorithm transformations for parallel processing and VLSI architecture design," Ph.D. dissertation, Univ. of Southern California, Los Angeles, Dec. 1983.
[6] L. J. Guibas, H. T. Kung, and C. D. Thompson, "Direct VLSI implementation of combinational algorithms," inProc. Caltech Conf. VLSI, 1979.
[7] C. Guerra and R. Melhem, "Synthesizing nonuniform systolic designs," inProc. Int. Conf. Parallel Processing, 1986.
[8] F. C. Hennie,Iterative Arrays of Logical Circuits. M.I.T. Press and Wiley, 1961.
[9] H. T. Kung and C. E. Leiserson, "Systolic arrays for VLSI," inIntroduction to VLSI Systems, C. A. Mead and L. A. Conway, Eds. Reading, MA: AddisonWesley, 1980, sect. 8.3.
[10] R. Karp, R. Miller, and S. Winograd, "The Organization of Computations for Uniform Recurrence Equations,"J. ACM, Vol. 14, No. 3, 1967, pp. 563590.
[11] R. H. Kuhn, "Efficient mapping of algorithms to singlestage interconnections," inProc. Seventh Annu. Symp. Comput. Architecture, 1980, pp. 182189.
[12] H. T. Kung and W. T. Lin, "An algebra for VLSI algorithm design," inProc. Conf. Elliptic Problem Solvers, 1983.
[13] S. Y. Kung, S. C. Lo, and P. S. Lewis, "Optimal systolic design for the transitive closure problem,"IEEE Trans. Comput., vol. C36, no. 5, pp. 603614, May 1987.
[14] H. T. Kung and M. S. Lam, "Waferscale integration and twolevel pipeline implementations,"J. Parallel Distributed Comput., vol. 1, no. 1, 1984.
[15] L. Lamport, "The parallel execution of DO loops,"Commun. ACM, vol. 17, no. 2, pp. 8393, Feb. 1974.
[16] W. M. Lin and V. K. Prasanna Kumar, "An extention to the linear transformation method with applications to systolizing the transitive closure problem," Tech. Rep., USC, 1987.
[17] G. J. Li and B. W. Wah, "The design of optimal systolic algorithms," inProc. Comput. Software Appl. Conf., 1983, pp. 310319.
[18] R. Melhem and C. Guerra, "The application of a sequence notation to the design of systolic computations," Tech. Rep. 568, Dep. Comput. Sci., Purdue Univ.
[19] D. I. Moldovan, "On the design of algorithms for VLSI systolic arrays,"IEEE Trans. Comput., vol. C31, pp. 11211126, 1982.
[20] W. L. Miranker and A. Winkler, "Spacetime representations of computational structures,"Computing, vol. 32, pp. 93114, 1984.
[21] V. K. Prasanna Kumar and Y. C. Tsai, "On mapping algorithm to linear and fault tolerant systolic arrays," inProc. ICCD, 1986.
[22] V. K. Prasanna Kumar and Y. C. Tsai, "On designing linear systolic arrays," USC Tech. Rep., 1986.
[23] S. K. Rao, "Regular iterative algorithms and their implementations on processor arrays," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1985.
[24] I. V. Ramakrishnan and P. J. Varman, "Synthesis of an optimal family of matrix multiplication algorithms on linear arrays," Tech. Rep., Dep. Comput. Sci. Univ. of Maryland, alsoProc. ICPP, 1985.
[25] C. Savage, "A systolic data structure chip for connectivity problems," inProc. CarnegieMellon Conf. VLSI Syst. Computat., Pittsburgh, PA, Oct. 1924. Rockville, MD: Computer Science Press, 1981, pp. 296300.
[26] B. P. Sinha, B. B. Bhattacharya, S. Ghose, and P. K. Srimani, "A parallel algorithm to compute the shortest paths and diameter of a graph and its VLSI implementation,"IEEE Trans. Comput., vol. C35, no. 11, pp. 10001004, 1986.
[27] J. Ullman,Computational Aspects of VLSI. Rockville, MD: Computer Science Press, 1983.
[28] F. L. Van Scoy, "The parallel recognition of classes of graphs,"IEEE Trans. Comput., vol. C29, no. 7, pp. 563570, 1980.
[29] P. J. Varman, and I. V. Ramakrishnan, "Dynamic programming and transitive closure on linear pipelines," inProc. ICPP, 1984.
[30] P. J. Varman, and I. V. Ramakrishnan, "Optimal matrix multiplication on faulttolerant VLSI arrays," inProc. ICALP, 1985.