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Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
March 1990 (vol. 39 no. 3)
pp. 360-374

Methods for designing self-testing checkers (STCs) for arithmetic error-detecting codes are presented. First, general rules for the design of minimal-level STCs for any error-detecting code are given. The design is illustrated with STCs for 3N+B codes, 0>or=B>or=2. Then the recursive structure of both 3N+B codes and residue/inverse-residue codes with check base A=3 is revealed. The resulting design of STCs is very flexible and universal, in the sense that an iterative, cost-effective, or high-speed version of the checker can be designed for either code. The design approach, unlike previous approaches for arithmetic codes, gives a unified treatment to STCs for nonseparate (3N+B) and separate (residue and inverse residue) codes. The speed and the complexity of the STC for a code from either class with n bits are about the same. Both high-speed checkers (which have up to three gate levels) and cost-effective checkers are faster and require less hardware than analogous checkers proposed for 3N codes and for residue codes with A=3.

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Index Terms:
self-testing checkers; arithmetic codes; error-detecting codes; complexity; gate levels; automatic testing; digital arithmetic; error detection codes; logic circuits; logic design; logic testing.
Citation:
S.J. Piestrak, "Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes," IEEE Transactions on Computers, vol. 39, no. 3, pp. 360-374, March 1990, doi:10.1109/12.48866
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