
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
T. Sasao, P. Besslich, "On the Complexity of Mod2l Sum PLA's," IEEE Transactions on Computers, vol. 39, no. 2, pp. 262266, February, 1990.  
BibTex  x  
@article{ 10.1109/12.45212, author = {T. Sasao and P. Besslich}, title = {On the Complexity of Mod2l Sum PLA's}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {2}, issn = {00189340}, year = {1990}, pages = {262266}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.45212}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  On the Complexity of Mod2l Sum PLA's IS  2 SN  00189340 SP262 EP266 EPD  262266 A1  T. Sasao, A1  P. Besslich, PY  1990 KW  mod2 sum PLA; computer simulation; complexity; logic functions; exclusiveOR; sumofproducts; ESOPs; upper bounds; minimality; symmetric functions; logic arrays; logic testing. VL  39 JA  IEEE Transactions on Computers ER   
Consideration is given to the realization of logic functions by using PLAs with an exclusiveOR (EXOR) array, where a function is represented by mod2 (EXOR) sumofproducts (ESOPs) and both true and complemented variables are used. The authors propose a new PLA structure using an EXOR array. They derive upper bounds on the number of products of this type of PLA that are useful for estimating the size of a PLA as well as for assessing the minimality of the solutions obtained by heuristic ESOP minimization algorithms. Computer simulation using randomly generated functions shows that PLAs with the EXOR array require, on the average, fewer products than conventional PLAs. For symmetric functions, the authors conjecture that the PLAs with an EXOR array require, at most, as many products as the conventional PLAs. The proposed PLAs can be made easily testable by adding a small amount of hardware.
[1] T. Sasao, "Multiplevalued decomposition of generalized Boolean functions and the complexity of programmable logic arrays,"IEEE Trans. Comput., vol. C30, pp. 635643, Sept. 1981.
[2] T. Sasao, "Input variable assignment and output phase optimization of PLA's,"IEEE Trans. Comput., vol. C33, pp. 879894, Oct. 1984.
[3] S. Even, I. Kohavi, and A. Paz, "On minimal modulo2 sums of products for switching functions,"IEEE Trans. Electron. Comput., vol. EC16, pp. 671674, Oct. 1967.
[4] A. Mukhopadhyay and G. Schmitz, "Minimization of Exclusive OR and logical equivalence of switching circuits,"IEEE Trans. Comput., vol. C19, pp. 132140, 1970.
[5] J. P. Robinson and C.L. Yeh, "A method for modulo2 minimization,"IEEE Trans. Comput., vol. C31, pp. 800801, 1982.
[6] P. Tirumalai and J. T. Butler, "On the realization of multiplevalued logic functions using CCD PLA's," inProc, 14 Int. Symp. MultipleValued Logic, May 1984, pp. 3342.
[7] G. W. Dueck and D. M. Miller, "A 4valued PLA using the MODSUM," inProc. 15 Int. Symp. MultipleValued Logic, May 1986, pp. 232240.
[8] T. Sasao and P. W. Besslich, "On the complexity of PLA's with EXOR arrays," IECEJ Tech. Rep., FTS 8617, Nov. 1986.
[9] I. S. Reed, "A class of multipleerrorcorrecting codes and their decoding scheme,"IRE Trans. Inform. Theory, vol. IT4, pp. 3849, Sept. 1954.
[10] D. E. Muller, "Application of Boolean algebra to switching circuit design and to error detection,"IRE Trans. Electron. Comput., vol. EC3, pp. 612, 1954.
[11] G. Bioul, M. Davio, and J. P. Deschamps, "Minimization of ringsum expansions of Boolean functions," Philips Res. Rep., vol. 28, pp. 1736, 1973.
[12] D. H. Green and I. S. Taylor, "Multiplevalued switching circuit design by means of generalized ReedMuller expansions,"Digital Processes, vol. 2, pp. 6381, 1976.
[13] P. W. Besslich and H. Bassmann, "Synthesis of ExclusiveOR logic functions," Berichte Elekrotechnik, ISSN 07241933, No. 3.87, Universitat Bremen, FB1, P.O. Box 330 440, D2800 Bremen 33, West Germany.
[14] P. W. Besslich, "Spectral processing of switching functions using signalflow transformations,"Spectral Techniques and Fault Detection, in M. Karpovsky, Ed. Orlando, FL: Academic, 1985, pp. 91141.
[15] S. J. Hong, R. G. Cain, and D. L. Ostapko, "MINI: A heuristic approach for logic minimization,"IBM J. Res. Develop., vol. 18, pp. 443458, Sept. 1974.
[16] H. Fleisher, M. Tavel, and J. Yeager, "A computer algorithm for minimizing ReedMuller canonical forms,"IEEE Trans. Comput., vol. C36, no. 2, pp. 247250, Feb. 1987.
[17] M. Helliwel and M. Perkowski, "A fast algorithm to minimize multioutput mixed polarity generalized ReedMuller forms," inProc. 25th Design Automat. Conf., June 1988, pp. 427432.
[18] T. Sasao and M. Higashida, "On a design algorithm for ANDEXOR PLA's with input decoders,"The 20th FTC Workshop, Jan. 1989 (in Japanese).
[19] M. A. Harrison,Introduction to Switching and Automata Theory. New York: McGrawHill, 1965.
[20] S. Muroga,Logic Design and Switching Theory. New York: Wiley, 1979.
[21] N. Koda and T. Sasao, "Table for minimum exclusiveOR sumofproducts for 4variable functions," in preparation.
[22] L. Hellerman, "A catalog of threevariable ORinvert and ANDinvert logical circuits,"IEEE Trans. Electron. Comput., vol. EC12, pp. 198223, June 1963.
[23] S. M. Reddy, "Easily testable realization for logic functions,"IEEE Trans. Comput., vol. C21, pp. 10831088, 1972.
[24] H. Fujiwara and K. Kinoshita, "A design procedure of programmable logic arrays with universal tests,"IEEE Trans. Comput., vol. C30, pp. 823828, Nov. 1981.
[25] K. A. Hua, J.Y. Jou, and J. A. Abraham, "Builtin tests for VLSI finitestate machines," inProc. IEEE 14th FaultTolerant Comput. Syst. Conf., 1984, pp. 292297.
[26] T. Sasao and H. Fujiwara, "A design of ANDEXOR PLA's with universal tests," IECEJ Tech. Rep., FTS 8626, Feb. 1987 (in Japanese).