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A VLSI Design for Computing Exponentiations in GF(2/sup m/) and its Application to Generate Pseudorandom Number Sequences
February 1990 (vol. 39 no. 2)
pp. 258-262

A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme.

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Index Terms:
VLSI design; computing exponentiations; pseudorandom number sequences; finite fields; logic CAD; multiplying circuits; random number generation; VLSI.
Citation:
C.C. Wang, D. Pei, "A VLSI Design for Computing Exponentiations in GF(2/sup m/) and its Application to Generate Pseudorandom Number Sequences," IEEE Transactions on Computers, vol. 39, no. 2, pp. 258-262, Feb. 1990, doi:10.1109/12.45211
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