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Extreme Area-Time Tradeoffs in VLSI
February 1990 (vol. 39 no. 2)
pp. 251-257

Consideration is given to the layout of bounded fan-in and fan-out prefix computation graphs in VLSI, and it is shown that the area requirements of such graphs exhibit this interesting property. A small constant factor reduction in time of computation from 2 log eta to log eta increases the area required to embed an eta node prefix computation graph significantly from O( eta log eta ) to Omega ( eta /sup 2/). The area requirements are also given. This behavior is an example of an extreme area-time tradeoff in VLSI. Since prefix computation also models the carry computation in a carry look-ahead adder, the same behavior is observed in the area requirements of a near-minimum computation time carry look-ahead adder. The authors also present circuits which meet the derived lower bounds for all values of T between log eta and 2 log eta .

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Index Terms:
layout; bounded fan-in; fan-out prefix computation graphs; area requirements; constant factor reduction; area-time tradeoff; carry look-ahead adder; lower bounds; circuit layout CAD; digital arithmetic; VLSI.
Citation:
B. Sugla, D.A. Carlson, "Extreme Area-Time Tradeoffs in VLSI," IEEE Transactions on Computers, vol. 39, no. 2, pp. 251-257, Feb. 1990, doi:10.1109/12.45210
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