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B. Sugla, D.A. Carlson, "Extreme AreaTime Tradeoffs in VLSI," IEEE Transactions on Computers, vol. 39, no. 2, pp. 251257, February, 1990.  
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@article{ 10.1109/12.45210, author = {B. Sugla and D.A. Carlson}, title = {Extreme AreaTime Tradeoffs in VLSI}, journal ={IEEE Transactions on Computers}, volume = {39}, number = {2}, issn = {00189340}, year = {1990}, pages = {251257}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.45210}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Extreme AreaTime Tradeoffs in VLSI IS  2 SN  00189340 SP251 EP257 EPD  251257 A1  B. Sugla, A1  D.A. Carlson, PY  1990 KW  layout; bounded fanin; fanout prefix computation graphs; area requirements; constant factor reduction; areatime tradeoff; carry lookahead adder; lower bounds; circuit layout CAD; digital arithmetic; VLSI. VL  39 JA  IEEE Transactions on Computers ER   
Consideration is given to the layout of bounded fanin and fanout prefix computation graphs in VLSI, and it is shown that the area requirements of such graphs exhibit this interesting property. A small constant factor reduction in time of computation from 2 log eta to log eta increases the area required to embed an eta node prefix computation graph significantly from O( eta log eta ) to Omega ( eta /sup 2/). The area requirements are also given. This behavior is an example of an extreme areatime tradeoff in VLSI. Since prefix computation also models the carry computation in a carry lookahead adder, the same behavior is observed in the area requirements of a nearminimum computation time carry lookahead adder. The authors also present circuits which meet the derived lower bounds for all values of T between log eta and 2 log eta .
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