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A Hardware Accelerator for Maze Routing
January 1990 (vol. 39 no. 1)
pp. 141-145

A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an increase in the number of processors as the problem size increases.

[1] S. B. Akers, Jr., "A modification of Lee's path connection algorithm,"IEEE Trans. Electron. Comput., vol. EC-16, pp. 97-98, Feb. 1967.
[2] T. Blank, M. Stefik, and W. van Cleemput, "A parallel bit map processor architecture for DA algorithms," inACM IEEE 18th DA Conf. Proc., pp. 837-845.
[3] T. Blank, "A survey of hardware accelerators used in computer-aided design,"IEEE Design Test. Comput., vol. 1, pp. 21-39, Aug. 1984.
[4] D.J. Chyan and M.A. Breuer, "A Placement Algorithm for Array Processors,"Proc. 20th Design Automation Conf., IEEE CS Press, Los Alamitos, Calif., Order No. M447 (microfiche), 1983, pp. 182-188.
[5] F. Gregoretti and Z. Segall, "Analysis and evaluation of VLSI design rule checking implementation in a multiprocessor," inProc. 1984 Int. Conf. Parallel Processing, Aug. 84, pp. 7-14.
[6] J. H. Hoel, "Some variations of Lee's algorithm,"IEEE Trans. Comput., vol. C-25, no. 1, pp. 19-24, Jan. 1976.
[7] A. Iosupovici, C. King, and M. Breuer, "A module interchange placement machine," inACM IEEE 20th DA Conf. Proc., pp. 171-174.
[8] A. Iosupovici, "A class of array architectures for hardware grid routers,"IEEE Trans. Comput.-Aided Design, vol. CAD-5, no. 2, pp. 245-255, Apr. 1986.
[9] R. Kane and S. Sahni, "A systolic design rule checker," inACM IEEE 21st DA Conf. Proc., pp. 243-250.
[10] C. Y. Lee, "An algorithm for path connections and its applications,"IRE Trans. EIectron. Comput., vol. EC-10, pp. 346-365, Sept. 1961.
[11] E. F. Moore, "Shortest path through a maze," inProc. Int. Symp. Theory Switching Circuits, inAnn. Harvard Computation Laboratory, vol. 30, pt. 2. Cambridge, MA: Harvard Univ. Press, 1959, pp. 285-292.
[12] T. N. Mudge, R. A. Rutenbar, R. M. Lougheed, and D. E. Atkins, "Celular image processing techniques for VLSI circuit layout validation and routing," inProc. 19th Design Automation Conf., June 1982.
[13] R. Nair, S. J. Hong, S. Liles, and R. Villani, "Global wiring on a wire routing machine," inACM IEEE 19th DA Conf. Proc., pp. 224-231.
[14] L. Seiler, "A hardware assisted design rule check architecture," inACM IEEE 19th DA Conf. Proc., pp. 232-238.
[15] J. Soukup, "Fast maze router," inProc. 15th Design Automat. Conf., Ottawa, Ont., Canada, June 1978, pp. 100-102.
[16] K. Ueda, T. Komatsubara, and T. Hosaka, "A parallel processing approach for logic module placement,"IEEE Trans. Comput.-Aided Design, vol. CAD-2, no. 1, pp. 39-47, Jan. 83.

Index Terms:
banked memory; hardware accelerator; maze routing; three-stage pipelines; circuit layout CAD.
Y. Won, S. Sahni, Y. El-Ziq, "A Hardware Accelerator for Maze Routing," IEEE Transactions on Computers, vol. 39, no. 1, pp. 141-145, Jan. 1990, doi:10.1109/12.46291
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