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A Hardware Accelerator for Maze Routing
January 1990 (vol. 39 no. 1)
pp. 141-145

A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an increase in the number of processors as the problem size increases.

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Index Terms:
banked memory; hardware accelerator; maze routing; three-stage pipelines; circuit layout CAD.
Citation:
Y. Won, S. Sahni, Y. El-Ziq, "A Hardware Accelerator for Maze Routing," IEEE Transactions on Computers, vol. 39, no. 1, pp. 141-145, Jan. 1990, doi:10.1109/12.46291
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