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Optimal Robust Compression of Test Responses
January 1990 (vol. 39 no. 1)
pp. 138-141

A compression of test responses technique for a built-in self-test (BIST) VLSI design is presented. The authors introduce the notion of a robust compression technique which incorporates prior knowledge of the statistics of fault-free responses under pseudorandom testing to achieve a guaranteed error detectability independent of a distribution of errors. The presented robust quadratic compressor requires two r-bit registers (r-bit signature) more than a multiple-input linear feedback shift register; however, it provides for equal protection against all error patterns. Therefore, quadratic compressors are optimal and robust with respect to a statistics of errors in a device under test.

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Index Terms:
optimal robust compression; test responses; built-in self-test; VLSI design; statistics; fault-free responses; pseudorandom testing; error detectability; automatic testing; data compression; integrated circuit testing; logic testing; VLSI.
Citation:
M.G. Karpovsky, P. Nagvajara, "Optimal Robust Compression of Test Responses," IEEE Transactions on Computers, vol. 39, no. 1, pp. 138-141, Jan. 1990, doi:10.1109/12.46290
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