Issue No.01 - January (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.46290
<p>A compression of test responses technique for a built-in self-test (BIST) VLSI design is presented. The authors introduce the notion of a robust compression technique which incorporates prior knowledge of the statistics of fault-free responses under pseudorandom testing to achieve a guaranteed error detectability independent of a distribution of errors. The presented robust quadratic compressor requires two r-bit registers (r-bit signature) more than a multiple-input linear feedback shift register; however, it provides for equal protection against all error patterns. Therefore, quadratic compressors are optimal and robust with respect to a statistics of errors in a device under test.</p>
optimal robust compression; test responses; built-in self-test; VLSI design; statistics; fault-free responses; pseudorandom testing; error detectability; automatic testing; data compression; integrated circuit testing; logic testing; VLSI.
M.G. Karpovsky, P. Nagvajara, "Optimal Robust Compression of Test Responses", IEEE Transactions on Computers, vol.39, no. 1, pp. 138-141, January 1990, doi:10.1109/12.46290