Issue No.01 - January (1990 vol.39)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.46281
<p>The organization of interleaved memories in such a way that faults in the memory system degrade the performance in a graceful manner is studied. Attention is restricted to an interleaved memory system that starts out with 2/sup q/ memory banks and uses a low-order interleaving scheme. The motivation and design objectives of the memory system are described. A new reconfiguration scheme and the design of the hardware needed to implement it are presented. The reconfiguration scheme is evaluated using trace-driven simulation for a number of benchmarks. The ideas presented can easily be extended to other interleaved memory schemes.</p>
gracefully degrading interleaved memory system; interleaved memories; reconfiguration scheme; trace-driven simulation; digital storage; fault tolerant computing.
G.S. Sohi, K.K. Salvia, K.C. Cheung, "Design and Analysis of a Gracefully Degrading Interleaved Memory System", IEEE Transactions on Computers, vol.39, no. 1, pp. 63-71, January 1990, doi:10.1109/12.46281