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Issue No.10 - October (1989 vol.38)
pp: 1460-1462
ABSTRACT
One of the techniques used to tackle the increasing complexity of testing VLSI circuits is to incorporate built-in self-test (BIST) structures. However, incorporation of such BIST structures calls for increased area overhead due to additional logic gates and interconnections. It is very important to keep this area overhead to a minimum. The authors present a simple graph model of the area overh
INDEX TERMS
testable VLSI; built-in self-test; logic gates; interconnections; graph model; automatic testing; integrated logic circuits; logic testing; VLSI.
CITATION
P.R. Chalasani, S. Bhawmik, A. Acharya, P. Palchaudhuri, "Design of Testable VLSI Circuits with Minimum Area Overhead", IEEE Transactions on Computers, vol.38, no. 10, pp. 1460-1462, October 1989, doi:10.1109/12.35841
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