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Design of Testable VLSI Circuits with Minimum Area Overhead
October 1989 (vol. 38 no. 10)
pp. 1460-1462
One of the techniques used to tackle the increasing complexity of testing VLSI circuits is to incorporate built-in self-test (BIST) structures. However, incorporation of such BIST structures calls for increased area overhead due to additional logic gates and interconnections. It is very important to keep this area overhead to a minimum. The authors present a simple graph model of the area overh

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[3] M. S. Abadir and M. A. Breuer, "A knowledge-based system for designing testable VLSI chips,"IEEE Design Test Comput., Aug. 1985.
[4] F. S. Hillier and G. J. Lieberman,Operations Research, 3rd ed. San Francisco, CA: Holden-Day, 1980.

Index Terms:
testable VLSI; built-in self-test; logic gates; interconnections; graph model; automatic testing; integrated logic circuits; logic testing; VLSI.
Citation:
P.R. Chalasani, S. Bhawmik, A. Acharya, P. Palchaudhuri, "Design of Testable VLSI Circuits with Minimum Area Overhead," IEEE Transactions on Computers, vol. 38, no. 10, pp. 1460-1462, Oct. 1989, doi:10.1109/12.35841
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