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Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor
June 1989 (vol. 38 no. 6)
pp. 874-880
The authors concentrate on design tradeoffs between the bit-serial multiplier and the full barrel shifter combined with a large register file. They analyze and compare three alternatives for a given set of technology related parameters and a given set of higher level language (HLL) benchmarks. Although their basic concern is the design of a 32-bit GaAs microprocessor on a single chip, the impli

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Index Terms:
microprocessors; design tradeoffs; bit-serial multiplier; full barrel shifter; large register file; GaAs microprocessor; single chip; 32 bits; logic design; microprocessor chips.
Citation:
V. Milutinovic, M. Bettinger, W. Helbig, "Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor," IEEE Transactions on Computers, vol. 38, no. 6, pp. 874-880, June 1989, doi:10.1109/12.24298
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