
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
S. Chakravarty, H.B. Hunt, III, S.S. Ravi, D.J. Rosenkrantz, "The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits," IEEE Transactions on Computers, vol. 38, no. 6, pp. 865869, June, 1989.  
BibTex  x  
@article{ 10.1109/12.24296, author = {S. Chakravarty and H.B. Hunt, III and S.S. Ravi and D.J. Rosenkrantz}, title = {The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits}, journal ={IEEE Transactions on Computers}, volume = {38}, number = {6}, issn = {00189340}, year = {1989}, pages = {865869}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.24296}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits IS  6 SN  00189340 SP865 EP869 EPD  865869 A1  S. Chakravarty, A1  H.B. Hunt, III, A1  S.S. Ravi, A1  D.J. Rosenkrantz, PY  1989 KW  complexity; minimum test sets; monotone combinational circuits; minimum complete test set; monotone PLAs; literals; NPcomplete; combinatorial circuits; computational complexity; logic arrays; logic testing. VL  38 JA  IEEE Transactions on Computers ER   
[1] V. K. Agarwal, "Multiple fault detection in PLA's," inProc. 9th Int. Conf. Fault Tolerant Comput., June 1979, pp. 227234.
[2] P. Bose and J. A. Abraham, "Test generation for programmable logic arrays," inProc. 19th Design Automat. Conf., Las Vegas, NV, June 1982, pp. 574580.
[3] R. Bentacourt, "Derivation of minimal test sets for unate logic circuits,"IEEE Trans. Comput., vol. C20, pp. 12641269, 1971.
[4] M. A. Breuer and A. D. Friedman,Diagnosis and Reliable Design for Digital Systems. Rockville, MD: Computer Science Press, 1976.
[5] C. W. Cha, "A test strategy for PLAS," inProc. 15th Design Automat. Conf., June 1978, pp. 326334.
[6] S. K. Chakravarty, H. B. Hunt III, S. S. Ravi, and D. J. Rosenkrantz, "The complexity of generating minimum test sets for PLA's and monotone combinational circuits," Tech. Rep. 8515, Dep. Comput. Sci., S.U.N.Y. Albany, 1985.
[7] R. Dandapani, "Derivation of minimal test sets for monotone logic circuits,"IEEE Trans. Comput., vol. C22, pp. 657661, 1973.
[8] W. H. Debaney, "On using the fanoutfree substructure of general combinational networks," Ph.D. dissertation, Syracuse Univ., 1985.
[9] E. B. Eichelberger and E. Lindbloom, "A heuristic test pattern generator for programmable logic arrays,"IBM J. Res. Develop., vol. 24. pp. 1522, Jan. 1980.
[10] H. Fujiwara and S. Toida, "The complexity of fault detection problems for combinational logic circuits,"IEEE Trans. Comput., vol. C31, pp. 555560, 1982.
[11] M. R. Garey and D. S. Johnson,Computers and Intractability: A Guide to Theory of NPCompleteness. San Francisco, CA: Freeman, 1979.
[12] S. Hassan and E. J. McClusky, "Testing PLA's using multiple parallel signature analyzers," inProc. 13th Symp. FaultTolerant Comput., 1983, pp. 422425.
[13] O. H. Ibarra and S. K. Sahni, "Polynomially complete fault detection problems,"IEEE Trans. Comput., vol. C24, pp. 242249, Mar. 1975.
[14] S. Jain and V. Agrawal. "STAFAN: An Alternative to Fault Simulation,"Proc. Design Automation Conf., 1984, pp. 1823.
[15] B. Krishnamurthy and S. B. Akers, "On the complexity of estimating the size of a test set,"IEEE Trans. Comput., vol. C33, pp. 750 753, Aug. 1984.
[16] E. I. Muehldorf and T. W. Williams, "Optimized stuckat fault test pattern generation for PLA macros," inDig. Semiconductor Test Symp., Oct. 1977, pp. 89101.
[17] D. L Ostapko and S. J. Hong, "Fault analysis and test generation for programmable logic arrays,"IEEE Trans. Comput., vol. C28, pp. 617627, Sept. 1979.
[18] S. M. Reddy and D. S. Ha, "A new approach to the design of testable PLA's,"IEEE Trans. Comput., vol. C36, pp. 201211, Feb. 1987.
[19] H. K. Reghbati, "Fault detection in PLA's,"IEEE Design Test Comput., vol. 3, pp. 4350, Dec. 1986.
[20] J. E. Smith, "Detection of faults in programmable logic arrays,"IEEE Trans. Comput., vol. C28, pp. 845853, Nov. 1979.
[21] R.S. Wei and A. SangiovanniVincentelli, "Platypus: A PLA Test Pattern Generation Tool,"Proc. Design Automation Conf., June 1985, pp. 197203.