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A Gracefully Degradable VLSI System for Linear Programming
June 1989 (vol. 38 no. 6)
pp. 853-861
The use of a fault-tolerant VLSI system for storing and solving linear programming problems is presented. The system can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. It is based on an interconnection pattern consisting of a complete binary tree in which spare links between cousin nodes are added so as to reconfigure it a

[1] I. Adler and R. Saigal, Eds., "Special Issue on Probabilistic Analysis of Simplex and Related Methods,"Math. Programming, vol. 35, June 1986.
[2] J. M. Atallah and S. R. Kosaraju, "A generalized dictionary machine for VLSI,"IEEE Trans. Comput., vol. C-34, pp. 151-155, Feb. 1985.
[3] A. A. Bertossi and M. A. Bonuccelli, "A VLSI implementation of the simplex algorithm,"IEEE Trans. Comput., vol. C-36, pp. 241-247, Feb. 1987.
[4] G. Bilardi and F. P. Preparata, "A minimum area VLSI network forO(logn) time sorting,"IEEE Trans. Comput., vol. C-34, no. 4, Apr. 1985.
[5] M. A. Bonncelliet al., "A VLSI tree machine for relational data bases," inProc. 10th Annu. Symp. Comput. Architecture, June 1983, pp. 67-73.
[6] R. P. Brent and H. T. Kung, "On the area of binary tree layouts,"Inform. Proc. Lett., vol. 11, pp. 44-46, Jan. 1980.
[7] J. A. B. Fortes and C. S. Raghavendra, "Gracefully degradable processor arrays,"IEEE Trans. Comput., vol. C-34, pp. 1033-1044, Nov. 1985.
[8] J. W. Greene and A. El Gamal, "Configuration of VLSI arrays in the presence of defects,"J. ACM, vol. 31, no. 4, pp. 694-717, 1984.
[9] B. O. A. Grey, A. Avizienis, and D. A. Rennels, "A fault-tolerant architecture for network storage systems," inProc. 14th FTCS Conf., 1984, pp. 232-239.
[10] A. S. M. Hassan and V. K. Agarwal, "A fault tolerant modular architecture for binary trees,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 356-361, Apr. 1986.
[11] D. K. Hsiao, "Database computers," inAdvances in Computers, Vol. 19, M. C. Yovits, Ed. New York: Academic, 1982.
[12] F. T. Leighton and C. E. Leiserson, "Wafer-scale integration of systolic arrays,"IEEE Trans. Comput., vol. C-34, pp. 448-461, May 1985.
[13] R. Negrini, M. Sami, and Stefanelli, "Fault tolerance techniques for array structures used in supercomputing,"IEEE Comput. Mag., pp. 78-87, Feb. 1986.
[14] T. A. Ottman, A. L. Rosenberg, and L. J. Stockmeyer, "A dictionary machine (for VLSI),"IEEE Trans. Comput., vol. C-31, pp. 892- 898, Sept. 1982.
[15] C. H. Papadimitriou and K. Steiglitz,Combinatorial Optimization: Algorithms and Complexity. Englewood Cliffs, NJ: Prentice-Hall, 1982.
[16] F. P. Preparata and J. Vuillemin, "Area-time optimal VLSI networks for multiplying matrices,"Inform. Proc. Lett., vol. 11, pp. 77-80, Oct. 1980.
[17] F. P. Preparata and J. Vuillemin, "Area-time optimal VLSI networks for computing integer multiplication and discrete Fourier transform," inProc. ICALP Conf., Haifa, Israel, 1981, pp. 39-40.
[18] C. S. Raghavendra, A. Avizienis, and M. Ercegovac, "Fault-tolerance in binary tree architectures,"IEEE Trans. Comput., vol. C-33, pp. 568-572, June 1984.
[19] A. L. Rosenberg, "The Diogenes approach to testable fault-tolerant arrays of processors,"IEEE Trans. Comput., vol. C-32, pp. 902- 910, Oct. 1983.
[20] A. L. Rosenberg, "A hypergraph model for fault-tolerant VLSI processor arrays,"IEEE Trans. Comput., vol. C-34, pp. 578-584, June 1985.
[21] A. K. Somani and V. K. Agarwal, "An efficient unsorted VLSI dictionary machine,"IEEE Trans. Comput., vol. C-34, pp. 841-852, Sept. 1985.
[22] C. D. Thompson, "The VLSI complexity of sorting,"IEEE Trans. Comput., vol. C-32, pp. 1171-1184, Dec. 1983.
[23] J. D. Ullman,Computational Aspects of VLSI. Rockville, MD: Computer Science Press, 1984.
[24] P. J. Varman and D. S. Fussell, "Realizing fault-tolerant binary trees in VLSI," inProc. 12th Allerton Conf. Commun., Comput., Contr., 1982, pp. 1008-1017.
[25] P. J. Varman, I. V. Ramakrishnan, and D. S. Fussell, "A robust matrix-multiplication array,"IEEE Trans. Comput., vol. C-33, pp. 919-922, Oct. 1984.

Index Terms:
gracefully degradable; fault-tolerant VLSI system; linear programming problems; multiple faults; interconnection pattern; complete binary tree; cousin nodes; ternary tree; faulty processing elements; simplex algorithm; computational complexity; fault tolerant computing; linear programming; VLSI.
Citation:
A.A. Bertossi, M.A. Bonuccelli, "A Gracefully Degradable VLSI System for Linear Programming," IEEE Transactions on Computers, vol. 38, no. 6, pp. 853-861, June 1989, doi:10.1109/12.24294
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