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CPC (Cyclic Pipeline Computer)-an Architecture Suited for Josephson and Pipelined-Memory Machines
June 1989 (vol. 38 no. 6)
pp. 825-832
Describes a novel computer architecture, called a cyclic pipeline computer (CPC), which is especially suited for Josephson technologies. Since each Josephson logic device acts as a latch, it is possible to use high-pitch and shallow logic pipelining without any increase in delay time and cost. Hence, both the processor and the main memory can be built from the Josephson devices and can be pipel

[1] E. Goto, T. Soma, N. Inada, T. Ida, M. Idesawa, K. Hiraki, M. Suzuki, K. Shimizu, and B. Philipov, "Design of a Lisp machine-FLATS," inConf. Rec. 1982 ACM Symp. LISP and Functional Programming., Pittsburgh, PA, Aug. 1982, pp. 208-215.
[2] E. Goto, "Josephson pairs device (DCFP)," (in Japanese) inProc. Riken Symp. Josephson Electron., Wako-shi, Mar. 1984, pp. 48- 58.
[3] E. Goto and K. Shimizu, "Architecture of a Josephson computer (FLATS-2)," inProc. 2nd Int. Symp. Symbolic Algebraic Computat. Comput. Singapore: World Scientific, 1985.
[4] Y. Harada, H. Nakane, N. Miyamoto, U. Kawabe, E. Goto, and T. Soma, "Basic operations of the quantum flux parametron,"IEEE Trans. Magn., vol. MAG-23, pp. 3801-3807, Sept. 1987.
[5] J.S. Kowalik, ed.,Parallel MIMD Computation: The HEP Supercomputer and Its Applications, MIT Press, Cambridge, Mass., 1985.
[6] K. F. Loe and E. Goto, "Analysis of flux input and output Josephson pair device,"IEEE Trans. Magn., vol. MAG-21, pp. 884-887, Mar. 1985.
[7] K. F. Loe and E. Goto,DC Flux Parametron--A New Approach to Josephson Logic. Singapore: World Scientific, 1986.
[8] K. Ogiue, M. Odaka, I. Masuda, T. Ikeda, T. Yasui, Y. Suzuki, and H. Uchida, "A 15 ns/250 mW 64 K static RAM," inProc. IEEE Int. Conf. Comput. Design, Oct. 1985. pp. 17-20.
[9] C. V. Ramamoorthy and H. F. Li, "Pipeline architecture."ACM Comput. Surveys, vol. 9, pp. 61-102, Mar. 1977.
[10] J. P. Riganati and P. B. Schneck, "Supercomputing,"IEEE Comput. Mag., vol. 17, no. 10, pp. 97-113, Oct. 1984.
[11] K. Shimizu, "High-performance computer architecture, Ph.D. dissertation, Dep. Inform. Sci., Faculty of Science, Univ. of Tokyo, 1985.
[12] K. Shimizu, "Logic simulation system for development of FLATS machine," inProc. RIMS Symp. Software Sci. Eng.Berlin, Germany, Springer-Verlag, 1986.
[13] C. Temperson, "Fast fourier transforms and Poisson solvers on Cray-I," inInfotech State of the Art Report Supercomputers Vol. 2, Berkshire, England, 1979, pp. 359-379.
[14] H. H. Zappe, "Josephson quantum interference computer devices,"IEEE Trans. Magn., vol. MAG-13, pp. 41-47, Jan. 1977.

Index Terms:
CPC; cyclic pipeline computer; architecture; pipelined-memory machines; Josephson technologies; MIMD; time-sharing; multiple instruction streams; parallel architectures.
Citation:
K. Shimizu, E. Goto, S. Ichikawa, "CPC (Cyclic Pipeline Computer)-an Architecture Suited for Josephson and Pipelined-Memory Machines," IEEE Transactions on Computers, vol. 38, no. 6, pp. 825-832, June 1989, doi:10.1109/12.24291
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