
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
T.R. Damarla, M. Karpovsky, "Fault Detection in Combinational Networks by ReedMuller Transforms," IEEE Transactions on Computers, vol. 38, no. 6, pp. 788797, June, 1989.  
BibTex  x  
@article{ 10.1109/12.24287, author = {T.R. Damarla and M. Karpovsky}, title = {Fault Detection in Combinational Networks by ReedMuller Transforms}, journal ={IEEE Transactions on Computers}, volume = {38}, number = {6}, issn = {00189340}, year = {1989}, pages = {788797}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.24287}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Fault Detection in Combinational Networks by ReedMuller Transforms IS  6 SN  00189340 SP788 EP797 EPD  788797 A1  T.R. Damarla, A1  M. Karpovsky, PY  1989 KW  ReedMuller transforms; fault detection; combinational networks; upper bound; multiple stuckatfaults; single bridging faults; time complexity; test patterns; test generation; combinatorial circuits; computational complexity; logic testing. VL  38 JA  IEEE Transactions on Computers ER   
[1] D. M. Miller and J. C. Muzio, "Spectral techniques for fault detection," inProc. 12th Int. Symp. Fault Tolerant Comput., 1982, pp. 152158.
[2] D. M. Miller and J. C. Muzio, "Spectral fault signatures for internally unate combinational networks,"IEEE Trans. Comput., vol. C32, pp. 10581062, 1983.
[3] D. M. Miller and J. C. Muzio, "Spectral fault signatures for single stuckatfaults in combinational networks,"IEEE Trans. Comput., vol. C33, pp. 765769, 1984.
[4] A. K. Susskind, "Testing by verifying Walsh coefficients,"IEEE Trans. Comput., vol. C32, pp. 198201, 1983.
[5] S. M. Reddy, "Easily testable realizations for logic functions,"IEEE Trans. Comput., vol. C21, pp. 11831188, Nov. 1972.
[6] K. K. Saluja and S. M. Reddy, "Fault detecting test sets for ReedMuller canonic networks,"IEEE Trans. Comput., vol. C24, pp. 995998, 1975.
[7] W. C. Carter, "Signature testing with guaranteed bounds for fault coverage," inDig. Papers Int. Test Conf., IEEE, Nov. 1982, pp. 75 82.
[8] S. B. Akers, "A parity bit signature for exhaustive testing," inDig. Papers Int. Test Conf., IEEE, Sept. 1986, pp. 4853.
[9] J. G. Kuhl and S. M. Reddy, "On the detection of stuckatfaults,"IEEE Trans. Comput., vol. C27, pp. 467469, May 1978.
[10] M. G. Karpovsky and L. B. Levitin, "Universal testing of computer hardware," inSpectral Techniques and Fault Detection, M. G. Karpovsky, ed. Orlando, FL: Academic, 1985.
[11] L. T. Fisher, "Unateness properties of ANDEXCLUSIVEOR logic circuits,"IEEE Trans. Comput., vol. C23, pp. 166172, Feb. 1974.
[12] M. G. Karpovsky,Finite Orthogonal Series in the Design of Digital Devices. New York: Wiley, 1976.
[13] D. M. Miller and J. C. Muzio, "Spectral techniques for fault detection in combinational logic," inSpectral Techniques and Fault Detection, M. Karpovsky, Ed. Orlando, FL: Academic, 1985.
[14] K. K. Slauja and E. H. Ong, "Minimization of ReedMuller canonic expansion,"IEEE Trans. Comput., vol. C28, pp. 535537, 1979.
[15] Ph. W. Besslich, "Spectral processing of switching functions using signalflow transformations," inSpectral Techniques and Fault Detection, M. G. Karpovsky, Ed. Orlando, FL: Academic, 1985.
[16] X. Wu, X. Chen, and S. L. Hurst, "Mapping of ReedMuller coefficients and the minimisation of ExclusiveOR switching functions,"Proc. IEE, vol. E129, pp. 1520, 1982.
[17] Y. Z. Zhang and P. J. W. Rayner, "Minimization of ReedMuller polynomials with fixed polarity,"Proc. IEE, vol. E131, pp. 177 186, Sept. 1984.
[18] T. Damarla and M. Karpovsky, "ReedMuller transforms for fault detections," inProc. 2nd Int. Workshop Spectral Techniques, Ecole Polytechnique de Montreal, Montreal, P. Q., Canada. Oct. 1986.
[19] T. Damarla, "ReedMuller transforms and their applications for fault detections," Ph.D. dissertation, Boston University, 1987.
[20] J. H. van Lint,Introduction to Coding Theory. New York: SpringerVerlag, 1982.
[21] W. W. Peterson and E. J. Weldon, Jr.,Error Correcting Codes. Cambridge, MA: MIT Press, 1984.
[22] H. Fujiwara and K. Kinoshita, "A design of programmable logic arrays with universal tests,"IEEE Trans. Comput., vol. C30, pp. 823838, 1981.
[23] K. Son and D. K. Pradhan, "Design of programmable logic arrays for testability," inProc. IEEE Test Conf., 1980, pp. 163166.
[24] S. L. Wang and A. Avizienis, "The design of totally self checking circuits using programmable logic arrays," inProc. Int. Symp. FTCS, 1979, pp. 173180.