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On the Optimal Design of Multiple-Valued PLAs
April 1989 (vol. 38 no. 4)
pp. 582-592
A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. Type 3 PLAs are the same as type 2 PLAs except for the use of 2-bit deco

[1] E. A. Bender, J. T. Butler, and H. G. Kerkhoff, "Comparing the sum with the max for use in four-valued PLA's," inProc. ISMVL-85, May 1985, pp. 30-35.
[2] R. G. Daniels and W. C. Bruce, "Built-in self-test trends in Motorola microprocessors,"IEEE Design Test, pp. 64-71, Apr. 1985.
[3] J. A. Darringer and W. H. Joyer, Jr., "A new look-at logic synthesis," inProc. 17th Design Automat. Conf. 1980, pp. 543-549.
[4] A. J. de Geus and W. Cohen, "Optimization of combinational logic using a rule based expert system,"J. IEEE Design Test, Aug. 1985, pp. 22-32.
[5] H. Fleisher, "The implementation and use of multivalued logic in a VLSI environment," inProc. ISMVL-83, May 1983, pp. 138-143.
[6] D. A. Freitas and K. W. Current, "CMOS circuit for quaternary encoding and decoding," inProc. ISMVL-84, May 1984, pp. 164- 168.
[7] S. J. Hong, R. G. Cain, and D. L. Ostapko, "MINI: A heuristic approach for logic minimization,"IBM J. Res. Develop., pp. 443- 458, Sept. 1974.
[8] S. L. Hurst, "Multiple-value logic: Its status and its future,"IEEE Trans. Comput., vol. C-33, pp. 1160-1179, Dec. 1984.
[9] M. Imme and C. A. Papachristou, "Simplification of MVL functions and implementation via a VLSI array structure," inProc. ISMVL-85, May 1985, pp. 242-248.
[10] M. Kameyama, T. Hanyu, M. Esashi, T. Higuchi, and T. Ito, "Implementation of quaternary NMOS integrated circuits for pipelined image processing," inProc. ISMVL-85, May 1985, pp. 226-232.
[11] H-L Kuo and K-Y Fang, "The multiple-valued programmable logic array and its application in modular design" inProc. ISMVL-85, May 1985, pp. 10-18.
[12] H. F. Law and M. Shoji, "PLA design of the BELLMAC-32A microprocessor," inProc. ICCC-82, 1982, pp. 161-164.
[13] E. J. McCluskey, "Logic design of MOS ternary logic," inProc. ISMVL-80, June 1980, pp. 1-5.
[14] S. Powell, E. Iodice, and E. Friedman, "An automated, low power, high speed complementary PLA design system for VLSI application," inProc. ICCD-84, 1984, pp. 314-319.
[15] R. Rudell and A. L. M. Sangiovanni-Vincentelli, "ESPRESSO-MV: Algorithms for multiple-valued logic minimization," inProc. 1985 Custom Integrated Circuits Conf., May 1985, pp. 230-234.
[16] T. Sasao, "Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays,"IEEE Trans. Comput., vol. C-30, pp. 635-643, Sept. 1981.
[17] T. Sasao, "Input variable assignment and output phase optimization of PLA's,"IEEE Trans. Comput., vol. C-33, pp. 879-894, Oct. 1984.
[18] T. Sasao,Programmable Logic Array: How to make and How to Use, (in Japanese) Tokyo, Japan, NIKKAN KOGYOU, May, 1986.
[19] T. Sasao, "MACDAS: Multi-level AND-OR Circuit Synthesis Using Two-Variable Function Generators,"Proc. Design Automation Conf., 1986, pp. 86-93.
[20] W. R. Smith, III, "Minimization of multivalued functions," inComputer Science and Multiple-Valued Logic, D. C. Rine Ed. New York: North Holland, 1977.
[21] P. Tirumalai and J. T. Butler, "On the realization of multiple-valued logic functions using CCD PLA's," inProc. ISMVL-84, May 1984, pp. 33-42, and Addendum distributed at ISMVL-84.
[22] C. Zukeran, C. Afuso, M. Kameyama, and T. Higuchi, "Design of new low-power quaternary CMOS logic circuits based on multiple ion implants," inProc. ISMVL-85, May 1985, pp. 84-90.

Index Terms:
optimal design; multiple-valued PLAs; programmable logic arrays; literal functions; 2-bit decoders; permutation network; logic arrays; logic design; many-valued logics.
Citation:
T. Sasao, "On the Optimal Design of Multiple-Valued PLAs," IEEE Transactions on Computers, vol. 38, no. 4, pp. 582-592, April 1989, doi:10.1109/12.21150
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