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The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
April 1989 (vol. 38 no. 4)
pp. 567-581
It is shown that the binary de Bruijn multiprocessor network (BDM) can solve a wide variety of classes of problems. The BDM admits an N-node linear array, an N-node ring, (N-1)-node complete binary trees, ((3N/4)-2)-node tree machines, and an N-node one-step shuffle-exchange network, where N (=2/sup k/, k an integer) is the total number of nodes. The de Bruijn multiprocessor networks are proved

[1] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[2] H. T. Kung and C. E. Leiserson, "Systolic arrays for VLSI," inIntroduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley.
[3] R. P. Brent and H. T. Kung, "Systolic VLSI arrays for polynomial GCD computation," Tech. Rep., Carnegie-Mellon Univ., Mar. 1982.
[4] H. T. Kung, "The structures of parallel algorithms" inAdvances in Computers, Vol. 19, New York: Academic, 1980, pp. 65-112.
[5] P. E. Danielsson, "Serial/parallel convolvers,"IEEE Trans. Comput., vol. C-33, pp. 652-667, July 1984.
[6] H. T. Kung and M. S. Lam, "Fault-tolerant and two-level pipelining in VLSI systolic arrays," inProc. MIT Conf. Advance Res. VLSI, Jan. 1984.
[7] S. A. Browning, "The tree machine: A highly concurrent computing environment," Ph.D. dissertation, California Instit. of Technol., 1980.
[8] S. W. Song, "A highly concurrent tree machine for data base applications," inProc. 1980 Int. Conf. Parallel Processing, Aug. 1980, pp. 259-268.
[9] E. Horowitz and A. Zorat, "The binary tree as an interconnection network: Applications to multiprocessor systems and VLSI,"IEEE Trans. Comput., vol. C-30, pp. 247-253, Apr. 1981.
[10] J. Bently and H. T. Kung, "A tree machine for searching problems," inProc. 1979 Int. Conf. Parallel Processing, Aug. 1979, pp. 257- 266.
[11] H. S. Stone, "Parallel processing with the perfect shuffle,"IEEE Trans. Comput., vol. C-20, pp. 153-161, Feb. 1971.
[12] T. Lang, "Interconnection between processing and memory modules using the shuffle-exchange network,"IEEE Trans. Comput., vol. C-25, pp. 55-66, Jan. 1976.
[13] D. S. Parker, "Notes on shuffle-exchange type switching networks,"IEEE Trans. Comput., vol. C-29, pp. 213-222, Mar. 1980.
[14] D. Kleitman, F. T. Leighton, M. Lepley, and G. L. Miller, "New layouts for the shuffle exchange graph," inProc. ACM Symp. Theory Computing, 1981, pp. 278-292.
[15] F. P. Preparata and J. Vuillemin, "The cube-connected cycle: A versatile network for parallel computation,"Commun. ACM, vol. 24, pp. 300-309, May 1981.
[16] C. D. Thompson and H. T. Kung, "Sorting on a mesh connected processor array,"Commun. ACM, pp. 263-271, 1972.
[17] W. E. Leland, "Density and reliability of interconnection topologies for multicomputers," Ph.D. dissertation, Univ. Wisconsin, Madison, May 1982.
[18] D. D. Nath, S. N. Maheshwari, and P. C. P. Bhatt, "Efficient VLSI networks for parallel processing based on orthogonal trees,"IEEE Trans. Comput., vol. C-32, pp. 569-581, June 1983.
[19] C. H. Sequin, "Double twisted torus networks for VLSI processor arrays," inProc. 8th Int. Symp. Comput. Architecture, May 1981, pp. 471-550.
[20] N. G. de Bruijn, "A combinatorial problem," Koninklijke Netherlands: Academe Van Wetenschappen,Proc. Vol. 49, part 20, 1946, pp. 758-764.
[21] M. L. Schlumberger, "DeBruijn communication networks," Ph.D. dissertation, Stanford Univ., Stanford, 1974.
[22] M. Imase and M. Itoh, "Design to minimize diameter on building-block networks,"IEEE Trans. Comput., vol. C-30, pp. 439-443, June 1981.
[23] D. K. Pradhan and S. M. Reddy, "A fault-tolerant communication architecture for distributed systems,"IEEE Trans. Comput., vol. C-31, pp. 863-870, Sept. 1982.
[24] M. R. Garey and D. S. Johnson,Computers and Intractability: A Guide to Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
[25] T. Etzion and A. Lempel, "Algorithms for the generation of full-length shift-register sequences,"IEEE Trans. Inform. Theory, vol. IT-30, pp. 244-251, May 1984.
[26] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Dep. Comput. Sci., Carnegie Mellon Univ., 1980.
[27] L. Synder, "Introduction to the configurable highly parallel computer,"IEEE Computer, pp. 47-56, Jan. 1982.
[28] J. L. Bentley, "Decomposable searching problem,"Inform. Processing Lett., vol. 8, pp. 244-251, June 1979.
[29] H. T. Kung, "Let's design algorithms for VLSI systems," inProc. Conf. Very Large Scale Integration: Architecture, Design and Fabrication, at California Institute of Technology, Jan. 1979.
[30] L. Haynes, R. Lau, D. Siewiorek, and D. Mizell, "A survey of highly parallel computing,"IEEE Computer, pp. 9-24, Jan. 1982.
[31] F. T. Leighton and C. E. Leiserson, "Wafer-scale integration of systolic arrays," inProc. 23rd IEEE Symp. Foundations Comput. Sci., pp. 297-311.
[32] P. Banerjee and J. A. Abraham, "Fault-secure algorithms for multiple processor systems," inProc. 11th Int. Symp. Comput. Architecture, June 1984, pp. 279-287.
[33] C. L. Seitz, "The Cosmic Cube,"Commun. ACM, pp. 22-33, Jan. 1985.
[34] A.-H. Esfahanian and S. L. Hakimi, "Fault-tolerant routing in de Bruijn communications networks,"IEEE Trans. Comput., vol. C-34, pp. 777-788, Sept. 1985.
[35] F. T. Leighton, "Optimal layouts for the shuffle-exchange graph and lower bound techniques for VLSI," Ph.D. dissertation, M.I.T., Aug. 1981.
[36] J. I. Raffelet al., "a wafer-scale integrator," inProc. Int. Conf. Comput. Design, Oct. 1984, pp. 212-126.
[37] A. Somani and V. Agarwal, "An unsorted dictionary machine for VLSI," inProc. 1984 Comput. Architecture Symp., 1984, pp. 142- 150.
[38] M. R. Samatham and D. K. Pradhan, "A multiprocessor network suitable for single-chip VLSI implementation," inProc. 11th Symp. Comput. Architect., June 1984, pp. 328-337.
[39] M. Ajtai, J. Komlos, and E. Szemeredi, "AnO(nlogn) sorting network," inProc. 15th ACM Symp. Theory Comput., 1983, pp. 1-9.
[40] K. E. Batcher, "Sorting networks and their applications," inProc. 1968 SJCC, AFIPS, vol. 32, 1968, pp. 307-314.
[41] T. C. Chen, V. Y. Lum, and C. Tung, "The rebound sorter: An efficient sort engine for large files," inProc. 1978 Int. Conf. Very Large Data Bases, 1978, pp. 312-318.
[42] D. E. Knuth,The Art of Computer Programming, Vol. 3, Reading, MA: Addison-Wesley, 1973.
[43] F.T. Leighton, "Tight bounds on the complexity of parallel sorting," inProc. 16th Annu. ACM Symp. Theory Computing, Washington, DC, May 1984, pp. 71-80.
[44] D. E. Muller and F. P. Preparata, "Bounds to complexities of networks for sorting and switching,"J. ACM, vol. 22, no. 2, Apr. 1975.
[45] D. Nassimi and S. Sahni, "Parallel permutation and sorting algorithms and a new generalized connection network,"J. ACM, vol. 29, no. 3, pp. 642-667, 1982.
[46] C. D. Thompson, "The VLSI complexity of sorting,"IEEE Trans. Comput., vol. C-32, Dec. 1983.
[47] L. E. Winslow and Y.-C. Chow, "The analysis and design of some new sorting machines,"IEEE Trans. Comput., vol. C-32, pp. 677- 683, July 1983.
[48] H. Yasuura, N. Takagi, and S. Yajima, "The parallel enumeration sorting scheme for VLSI,"IEEE Trans. Comput., vol. C-31, pp. 1192-1201, Dec. 1982.
[49] F. T. Leighton, private communication.
[50] M. R. Samathan and D. K. Pradhan, "The De Bruijn multiprocessor network: A versatile sorting network," inIEEE Proc. 12th Int. Symp. Comput. Architecture, Boston, MA, June 1985, pp. 360-367.

Index Terms:
de Bruijn multiprocessor network; versatile parallel processing; sorting network; VLSI; N-node linear array; N-node ring; binary trees; one-step shuffle-exchange network; tight lower bound; layout area; fault tolerant computing; multiprocessor interconnection networks; parallel processing; VLSI.
M.R. Samatham, D.K. Pradhan, "The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI," IEEE Transactions on Computers, vol. 38, no. 4, pp. 567-581, April 1989, doi:10.1109/12.21149
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