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Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
April 1989 (vol. 38 no. 4)
pp. 547-554
Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after

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Index Terms:
reconfiguration; distributed defects; VLSI/WSI mesh array processors; two-level redundancy; processing elements; parallel rectangular; complexity; manufacturing yield; operation reliability; optimization technique; combinatorial analysis; clustered defects; fault tolerant computing; parallel processing; VLSI.
Citation:
M. Wang, M. Cutler, S.H. Su, "Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy," IEEE Transactions on Computers, vol. 38, no. 4, pp. 547-554, April 1989, doi:10.1109/12.21147
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