This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
On Implementing Large Binary Tree Architectures in VLSI and WSI
April 1989 (vol. 38 no. 4)
pp. 526-537
The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown th

[1] J. Bentley and H. T. Kung, "A tree machine for searching problems," inProc. Int. Conf. Parallel Processing, Aug. 1979, pp. 257-266.
[2] M. A. Bonncelliet al., "A VLSI tree machine for relational data bases," inProc. 10th Annu. Symp. Comput. Architecture, June 1983, pp. 67-73.
[3] T. A. Ottman, A. L. Rosenberg, and L. J. Stockmeyer, "A dictionary machine (for VLSI),"IEEE Trans. Comput., vol. C-31, pp. 892- 898, Sept. 1982.
[4] A. M. Despain and D. A. Patterson, "X-tree: A tree structured multiprocessor computer architecture," inProc. Fifth Int. Symp. Comput. Architecture, Apr. 1978, pp. 144-151.Comput. Architecture, pp. 21-28, Dec. 1973.
[5] R. P. Brent and H. T. Kung, "On the area of binary tree layout,"Inform. Contr., vol. 65, pp. 45-52, 1982.
[6] M. S. Paterson, W. L. Ruzzo, and L. Snyder, "Bounds on minimax edge length for complete binary trees," inProc. 13th Annu. ACM Symp. Theory Comput., 1981, pp. 293-299.
[7] L. G. Valiant, "Universality considerations in VLSI circuits,"IEEE Trans. Comput., vol. C-30, pp. 135-140, Feb. 1981.
[8] H. Y. Youn and A. D. Singh, "On area efficient and fault tolerant tree embedding in VLSI," inProc. Int. Conf. Parallel Processing, 1987, pp. 171-178.
[9] E. Horowitz and A. Zorat, "The binary tree as an interconnection network: Applications to multiprocessor systems and VLSI,"IEEE Trans. Comput., vol. C-30, pp. 247-253, Apr. 1981.
[10] D. Gordonet al., "Embedding tree structures in VLSI hexagonal arrays,"IEEE Trans. Comput., vol. C-33, pp. 104-107, Jan. 1984.
[11] D. Gordon, "Efficient embeddings of binary trees in VLSI arrays,"IEEE Trans. Comput., vol. C-36, pp. 1009-1018, Sept. 1987.
[12] A. Mukhopadhyay and R. K. Guha, "Embedding a tree in the nearest neighbor array," inProc. Int. Conf. Parallel Processing, 1981, pp. 261-263.
[13] M. S. Lee and G. Frieder, "Massively fault-tolerant cellular array," inProc. Int. Conf. Parallel Processing, 1986, pp. 343-350.
[14] L. Snyder, "Introduction to the configurable, highly parallel computer,"IEEE Computer, vol. 15, pp. 47-56, Jan. 1982.
[15] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[16] J. F. McDonaldet al., "The trials of WSI,"IEEE Spectrum, pp. 32- 39, Oct. 1984.
[17] B. Chazelle and L. Monier, "A model of computation for VLSI with related complexity results," inProc. 13th ACM Symp. Theory Comput., 1981.
[18] A. D. Singh, "A reconfigurable modular fault tolerant binary tree architecture," inProc. 15th Annu. Symp. Fault Tolerant Comput., June 1987, pp. 298-303.
[19] A. D. Singh, "A modular binary tree architecture with shared spares,"IEEE Trans. Comput., to be published.
[20] M. B. Lowrie and W. K. Fuchs, "Reconfigurable tree architectures using subtree oriented fault tolerance,"IEEE Trans. Comput., vol. C-36, pp. 1172-1182, Oct. 1987.
[21] M. C. Howells and V. K. Agarwal, "Yield and reliability enhancement of large area binary tree architectures," inProc. 15th Annu. Symp. Fault Tolerant Comput., June 1987, pp. 290-295.
[22] A. L. Rosenberg, "The Diogenes approach to testable fault-tolerant arrays of processors,"IEEE Trans. Comput., vol. C-32, pp. 902- 910, 1983.
[23] T. Leighton and C. E. Leiserson, "Wafer scale integration of systolic arrays,"IEEE Trans. Comput., vol. C-34, pp. 448-461, May 1985.
[24] F. M. Rhodes, "Performance characteristics of the RVLSI technology," inProc. IFIP Workshop Wafer-Scale Integration, Genoble, 1986.
[25] W. L. Ruzzo and L. Snyder, "Minimum edge length planer embeddings of trees," inVLSI Systems and Computation, Kung, Sproull, and Steel, Eds. Rockville, MD: Computer Science, 1981.
[26] I. Koren, "A reconfigurable and fault-tolerant VLSI multiprocessor array," inProc. 8th Int. Symp. Comput. Architecture, Minneapolis, MN, May 1981, pp. 425-442.

Index Terms:
large binary tree architectures; VLSI; WSI; layout; two-dimensional array; processing elements; propagation delay; maximum edge length; H-tree layouts; fault-tolerant designs; circuit layout CAD; trees (mathematics); VLSI.
Citation:
H.Y. Youn, A.D. Singh, "On Implementing Large Binary Tree Architectures in VLSI and WSI," IEEE Transactions on Computers, vol. 38, no. 4, pp. 526-537, April 1989, doi:10.1109/12.21145
Usage of this product signifies your acceptance of the Terms of Use.