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Fault-Tolerant Array Processors Using Single-Track Switches
April 1989 (vol. 38 no. 4)
pp. 501-514
An array grid model based on single-track switches is proposed. A reconfigurability theorem is developed to provide the theoretical footing for novel reconfiguration algorithms for the fabrication-time and run-time processing. For fabrication-time yield enhancement, the problem of finding a feasible reconfiguration using global control can be reformulated as a maximum independent set problem. A

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Index Terms:
fabrication time processing; fault tolerant array processors; single-track switches; array grid model; reconfigurability theorem; run-time processing; yield enhancement; graph theory; propagation time; fault tolerant computing; graph theory; parallel processing.
S.-Y. Kung, S.-N. Jean, C.W. Chang, "Fault-Tolerant Array Processors Using Single-Track Switches," IEEE Transactions on Computers, vol. 38, no. 4, pp. 501-514, April 1989, doi:10.1109/12.21143
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