Issue No.04 - April (1989 vol.38)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.21141
The authors study the tolerance of defects faults in cache memories. They argue that, even though the major components of a cache are linear RAMs (random-access memories), traditional techniques used for fault/defect tolerance in RAMs may be neither appropriate nor necessary for cache memories. They suggest a scheme that allows a cache to continue operation in the presence of defective/faulty b
cache memory organization; yield; high performance VLSI processors; tolerance of defects faults; linear RAMs; trace-driven simulation analysis; performance degradation; buffer storage; fault location; integrated memory circuits; random-access storage; storage management chips; VLSI.
G.S. Sohi, "Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors", IEEE Transactions on Computers, vol.38, no. 4, pp. 484-492, April 1989, doi:10.1109/12.21141