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On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays
March 1989 (vol. 38 no. 3)
pp. 470-478
A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output

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Index Terms:
linear systolic arrays; algorithms; fault-tolerant systolic arrays; mapping technique; matrix computations; linearly connected arrays; processor elements; VLSI model; propagation delay; Diogenes methodology; cellular arrays; fault tolerant computing.
Citation:
V.K.P. Kumar, Y.-C. Tsai, "On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays," IEEE Transactions on Computers, vol. 38, no. 3, pp. 470-478, March 1989, doi:10.1109/12.21135
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