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B.P. Sinha, P.K. Srimani, "Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures," IEEE Transactions on Computers, vol. 38, no. 3, pp. 424431, March, 1989.  
BibTex  x  
@article{ 10.1109/12.21128, author = {B.P. Sinha and P.K. Srimani}, title = {Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures}, journal ={IEEE Transactions on Computers}, volume = {38}, number = {3}, issn = {00189340}, year = {1989}, pages = {424431}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.21128}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures IS  3 SN  00189340 SP424 EP431 EPD  424431 A1  B.P. Sinha, A1  P.K. Srimani, PY  1989 KW  parallel algorithms; binary multiplication; systolic architectures; nbit binary numbers; column compression; VLSI implementation; two's complement numbers; digital arithmetic; parallel algorithms. VL  38 JA  IEEE Transactions on Computers ER   
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