Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures
Issue No.03 - March (1989 vol.38)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.21128
Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time.
parallel algorithms; binary multiplication; systolic architectures; n-bit binary numbers; column compression; VLSI implementation; two's complement numbers; digital arithmetic; parallel algorithms.
B.P. Sinha, P.K. Srimani, "Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures", IEEE Transactions on Computers, vol.38, no. 3, pp. 424-431, March 1989, doi:10.1109/12.21128