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Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures
March 1989 (vol. 38 no. 3)
pp. 424-431
Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time.

[1] D. E. Knuth,The Art of Computer Programming, Vol. 2, Seminumerical Algorithms. Reading, MA: Addison-Wesley, 1981.
[2] C. S. Wallace, "A suggestion for a fast multiplier,"IEEE Trans. Electron. Comput., vol. EC-13, pp. 114-117, Feb. 1964.
[3] L. Dadda, "On parallel digital multipliers,"Alta Frequenza, vol. 45, pp. 574-580, 1976.
[4] W. J. Stenzel, W. J. Kubitz, and G. H. Garcia, "A compact high speed parallel multiplication scheme,"IEEE Trans. Comput., vol. C-26, pp. 948-957, Oct. 1977.
[5] J. P. Hayes,Computer Architecture and Organization. New York: McGraw-Hill, 1988.
[6] R. G. Hintz and D. P. Tate, "Control data STAR-100 processor design," inProc. 6th Annu. IEEE Comput. Soc, Int. Conf. (COMPCON 72), CA, Sept. 1972, pp. 1-4.
[7] S. Nakamura, "Algorithms for iterative array multiplication,"IEEE Trans. Comput., vol. C-35, pp. 713-719, Aug. 1986.
[8] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Dep. Comput. Sci., Carnegie Mellon Univ., 1980.
[9] T. Herman, "Linear algorithm that are efficiently parallelized to the timeO(logn)," Tech. Rep. TR-85-17, Dept. Comput. Sci., Univ. Texas, Austin, Sept. 1985.
[10] C. R. Baugh and B. A. Wooley, "A two's complement parallel array multiplication algorithm,"IEEE Trans. Comput., vol. C-22, pp. 1045-1059, Dec. 1973.
[11] N. Takagi, H. Yasuura, and S. Yajima, "High-speed VLSI multiplication algorithm with a redundant binary addition tree,"IEEE Trans. Comput., vol. C-34, no. 9, pp. 789-796, Sept. 1985.

Index Terms:
parallel algorithms; binary multiplication; systolic architectures; n-bit binary numbers; column compression; VLSI implementation; two's complement numbers; digital arithmetic; parallel algorithms.
Citation:
B.P. Sinha, P.K. Srimani, "Fast Parallel Algorithms for Binary Multiplication and their Implementation on Systolic Architectures," IEEE Transactions on Computers, vol. 38, no. 3, pp. 424-431, March 1989, doi:10.1109/12.21128
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