The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.03 - March (1989 vol.38)
pp: 394-407
ABSTRACT
A design strategy is presented for efficient and comprehensive parallel testing of high-density, MOS random-access memories (RAMs). Parallel test algorithms for RAMs have been developed on the basis of this design-for-testability approach for a broad class of pattern-sensitive faults. Two algorithms which are significantly more efficient than previous approaches are examined. The first algorith
INDEX TERMS
parallel testing; pattern-sensitive faults; semiconductor random-access memories; design strategy; MOS; design-for-testability approach; reliability; linear complexity; integrated circuit testing; integrated memory circuits; MOS integrated circuits; random-access storage.
CITATION
P. Mazumder, "Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories", IEEE Transactions on Computers, vol.38, no. 3, pp. 394-407, March 1989, doi:10.1109/12.21126
60 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool