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Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories
March 1989 (vol. 38 no. 3)
pp. 394-407
A design strategy is presented for efficient and comprehensive parallel testing of high-density, MOS random-access memories (RAMs). Parallel test algorithms for RAMs have been developed on the basis of this design-for-testability approach for a broad class of pattern-sensitive faults. Two algorithms which are significantly more efficient than previous approaches are examined. The first algorith

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Index Terms:
parallel testing; pattern-sensitive faults; semiconductor random-access memories; design strategy; MOS; design-for-testability approach; reliability; linear complexity; integrated circuit testing; integrated memory circuits; MOS integrated circuits; random-access storage.
Citation:
P. Mazumder, J.H. Patel, "Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories," IEEE Transactions on Computers, vol. 38, no. 3, pp. 394-407, March 1989, doi:10.1109/12.21126
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