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Issue No.03 - March (1989 vol.38)
pp: 385-393
ABSTRACT
The fault tolerance of multiprocessor systems with multistage interconnection networks under multiple faults in the network is studied. The fault tolerance is analyzed with respect to the criterion of dynamic full access (DFA) property of the processors in the system. A characterization of multiple faults in the Omega network is introduced and used to develop simple tests for the DFA capability
INDEX TERMS
fault tolerant routing; multistage interconnection networks; multiprocessor systems; multiple faults; Omega network; k-stage shuffle/exchange networks; processing elements; fault tolerant computing; multiprocessor interconnection networks.
CITATION
A. Varma, C.S. Raghavendra, "Fault-Tolerant Routing in Multistage Interconnection Networks", IEEE Transactions on Computers, vol.38, no. 3, pp. 385-393, March 1989, doi:10.1109/12.21125
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