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Circuit Simulation on Shared-Memory Multiprocessors
December 1988 (vol. 37 no. 12)
pp. 1634-1642
Reports the parallelization on a shared-memory vector multiprocessor of the computationally intensive components of a circuit simulator-matrix assembly (including device model evaluation) and the unstructured sparse linear system solution. A theoretical model is used to predict the performance of the lock-synchronized parallel matrix assembly, and the results are compared to experimental measur

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Index Terms:
shared-memory multiprocessors; parallelization; vector multiprocessor; sparse matrix solution; parallel implementation; circuit simulator; circuit CAD; digital simulation; parallel processing.
P. Sadayappan, V. Visvanathan, "Circuit Simulation on Shared-Memory Multiprocessors," IEEE Transactions on Computers, vol. 37, no. 12, pp. 1634-1642, Dec. 1988, doi:10.1109/12.9740
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