This Article 
 Bibliographic References 
 Add to: 
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
December 1988 (vol. 37 no. 12)
pp. 1578-1598
The mapping of algorithms structured as depth-p nested FOR loops into special-purpose systolic VLSI linear arrays is addressed. The mappings are done by using linear functions to transform the original sequential algorithms into a form suitable for parallel execution on linear arrays. A feasible mapping is derived by identifying formal criteria to be satisfied by both the original sequential al

[1] A. V. Aho, J. E. Hopcroft, and J. D. Ullman,The Design and Analysis of Computer Algorithms. Menlo Park, CA: Addison-Wesley, 1974.
[2] M. A. Annaratone, F. Bitz, E. Clune, H. T. Kung, P. Maulik, O. Menzilcioglu, H. Rabas, and J. A. Webb, "Applications and algorithm partitioning on WARP," inProc. IEEE COMPCON, Feb. 23-27, 1987, pp. 272-275.
[3] M. Annaraton, E. Arnould, T. Gross, H. Kung, M. Lam, O. Menzilcioglu, and J. Webb, "The Warp computer: Architecture, implementation, and performance,"IEEE Trans. Comput., vol. C-36, pp. 1523-1538, Dec. 1987.
[4] U. Banerjee, S. C. Chen, D. J. Kuck, and R. A. Towle, "Time and parallel processor bounds for FORTRAN like loops,"IEEE Trans. Comput., vol. C-28, pp. 660-670, Sept. 1979.
[5] R. P. Brent and H. T. Kung, "The area-time complexity of binary multiplication,"J. ACM, vol. 28, no. 3, pp. 521-534, 1981.
[6] M. C. Chen, "The generation of a class of multipliers: Synthesizing highly parallel algorithms in VLSI,"IEEE Trans. Comput., vol. C- 37, pp. 329-338, Mar. 1988.
[7] L. J. Guibas, H. T. Kung, and C. D. Thompson, "Direct VLSI implementation of combinatorial algorithms," inProc. CALTECH Conf. VLSI, Jan. 1979, pp. 509-525.
[8] B. Hochet, P. Quinton, and Y. Robert, "Systolic solution of linear systems overGF(p)with partial pivoting," IEEE CH2419-0, pp. 161- 168, 1987.
[9] C.-H. Huang, "The mechanically certified derivation of concurrency and application to systolic design," Ph.D. dissertation, Univ. Texas, Austin, TX, 1987.
[10] K. Hwang and Y. H. Cheng, "Partitioned matrix algorithms for VLSI arithmetic systems,"IEEE Trans. Comput., vol. C-31, pp. 1215- 1224, Dec. 1982.
[11] K. Hwang and F. A. Briggs,Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1984.
[12] R. Karp, R. Miller, and S. Winograd, "The Organization of Computations for Uniform Recurrence Equations,"J. ACM, Vol. 14, No. 3, 1967, pp. 563-590.
[13] Z. M. Kedem, "Optimal allocation of area for single-chip computations,"SIAM J. Comput., vol. 14, pp. 730-743, Aug. 1985.
[14] R. H. Kuhn, "Transforming algorithms for single-stage and VLSI architectures," inProc. Workshop Interconnection Networks Parallel Distributed Processing, IEEE CH1560-2, 1980, pp. 11-19.
[15] A. V. Kulkarni and D. W. L. Yen, "Systolic processing and an implementation for signal and image processing,"IEEE Trans. Comput., vol. C-31, pp. 1000-1009, Oct. 1982.
[16] H. T. Kung and C. E. Leiserson, "Systolic arrays for (VLSI)," CMU Tech. Rep. CMU-CS-79-103, Apr. 1978.
[17] H. T. Kung, "Let's design algorithms for VLSI systems," CMU Tech. Rep. CMU-C-79-151, Jan. 1979.
[18] H. T. Kung, "Why systolic architectures?."IEEE Computer, pp. 37-46, Jan. 1982.
[19] H. T. Kung, "Systolic algorithms for the CMU WARP processor," inProc. Seventh Int. Conf. Pattern Recognition, July 1984, pp. 570-577.
[20] S. Y. Kung, "On supercomputing with systolic/wavefront array processors,"Proc. IEEE, vol. 72, pp. 867-884, July 1984.
[21] S. Y. Kung, S. C. Lo, and P. S. Lewis, "Optimal systolic design for the transitive closure problem,"IEEE Trans. Comput., vol. C-36, no. 5, pp. 603-614, May 1987.
[22] L. Lamport, "The parallel execution of DO loops,"Commun. ACM, vol. 17, no. 2, pp. 83-93, Feb. 1974.
[23] P.-Z. Lee, "A new VLSI synthesis method," M.S. thesis, National Tsing-Hua Univ., Taiwan, Republic of China, 1984.
[24] P.-Z. Lee and Z. M. Kedem, "Synthesizing linear-array algorithms from nested for loop algorithms," NYU Comput. Sci. TR-355, Mar. 1988.
[25] P. Lee and Z.M. Kedem, "On High-Speed Computing with a Programmable Linear Array,"Proc. Supercomputing 88, Vol. 1, CS Press, Los Alamitos, Calif., Order No. 882, pp. 425-432.
[26] G. Li and B. W. Wah, "The design of optimal systolic arrays,"IEEE Trans. Comput., vol. C-34, pp. 66-77, Jan. 1985.
[27] Y. J. Ma, J. F. Wang, and J. Y. Lee, "Systolic array mapping of sequential algorithm for VLSI architecture," inProc. Int. Comput. Symp., Tainan, Taiwan, Republic of China, Dec. 1986, pp. 865-874.
[28] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[29] W. L. Miranker and A. Winkler, "Spacetime representations of computational structures,"Computing, vol. 32, pp. 93-114, 1984.
[30] D. I. Moldovan, "On the analysis of VLSI systems,"IEEE Trans. Comput., vol, C-31, pp. 1121-1126, Nov. 1982.
[31] D.I. Moldovan, "On the design of algorithms for VLSI systolic arrays,"Proc. IEEE, vol. 71, pp. 113-120, Jan. 1983.
[32] D. I. Moldovan and J. A. B. Fortes, "Partitioning and mapping algorithms into fixed size systolic arrays,"IEEE Trans. Comput., vol. C-35, pp. 1-12, Jan. 1986.
[33] D.I. Moldovan, "Advis: A Software Package for the Design of Systolic Arrays,"IEEE Trans. Computer-Aided Design, Jan. 1987, pp. 33-40.
[34] P. Quinton, "Automatic synthesis of systolic arrays from uniform recurrent equations," inProc. 11th Annu. Symp. Comput. Architecture, 1984, pp. 208-214.
[35] P. Quinton, "Mapping recurrences on parallel architectures," inProc. Third Int. Conf. Supercomputing, Boston, MA, May 15-20, 1988.
[36] S. K. Rao, "Regular iterative algorithms and their implementations on processor arrays," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1985.
[37] I. Ramakrishnan, D. Fussell, and A. Silberschatz, "A linear array matrix multiplication algorithm," inProc. 20th Annu. Allerton Conf. Comput., Contr., Commun., Oct. 1982.
[38] I. Ramakrishnan and P. Varman, "Modular matrix multiplication on a linear array,"IEEE Trans. Comput., vol. C-33, pp. 952-958, Nov. 1984.
[39] I. Ramakrishnan, D. Fussell, and A. Silberschatz, "Mapping homogeneous graphs on linear arrays,"IEEE Trans. Comput., vol. C-35, pp. 198-209, Mar. 1986.
[40] G. Rote, "A systolic array algorithm for the algebraic path problem,"Computing, vol. 34, pp. 191-219, 1985.
[41] C. D. Thompson, "Area-time complexity for VLSI," inProc. Eleventh Annu. ACM Symp. Theory Comput., 1979, pp. 81-88.
[42] J. D. Ullman,Computational Aspects of VLSI. Rockville, MD: Computer Science Press, 1984.
[43] P. Varman and I. Ramakrishnan, "Dynamic programming and transitive closure on linear pipelines," inProc. Int. Conf. Parallel Processing, 1984, pp. 359-364.
[44] P. Varman and I. Ramakrishnan, "On matrix multiplication using array processors," inProc. Automata, Languages Programming, 12th Colloquium, Nafplion, Greece, July 1985, pp. 487-496.
[45] P. Varman and I. Ramakrishnan, "A fault-tolerant VLSI matrix multiplier," Tech. Rep. 85/29, State Univ. New York, Stony Brook, Oct. 1985.
[46] I. V. Ramakrishnan and P. J. Varman, "Synthesis of an optimal family of matrix multiplication algorithms on linear arrays,"IEEE Trans. Comput., vol. C-35, no. 11, 1986.
[47] Y. Wong and J. Delosme, "Optimal systolic implementations of N-dimensional recurrences," inIEEE Proc. ICCD, 1985, pp. 618-621.
[48] C. B. Yang and R. C. T. Lee, "Systolic algorithms for the LCS problem," inProc. Int. Comput. Symp., Taipei, Taiwan, Republic of China, 1984, pp. 895-901.

Index Terms:
linear array algorithms; nested FOR loop algorithms; systolic VLSI linear arrays; mappings; parallel execution; parallel algorithms.
Lee Peizong, Z.M. Kedem, "Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms," IEEE Transactions on Computers, vol. 37, no. 12, pp. 1578-1598, Dec. 1988, doi:10.1109/12.9735
Usage of this product signifies your acceptance of the Terms of Use.