
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
P. Bose, "A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem," IEEE Transactions on Computers, vol. 37, no. 12, pp. 15691577, December, 1988.  
BibTex  x  
@article{ 10.1109/12.9734, author = {P. Bose}, title = {A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem}, journal ={IEEE Transactions on Computers}, volume = {37}, number = {12}, issn = {00189340}, year = {1988}, pages = {15691577}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.9734}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem IS  12 SN  00189340 SP1569 EP1577 EPD  15691577 A1  P. Bose, PY  1988 KW  parallel implementation; logic/fault simulation; VLSI; array logic; vector parallel; logic arrays; logic CAD; parallel processing. VL  37 JA  IEEE Transactions on Computers ER   
[1] T. Blank, "A survey of hardware accelerators used in computeraided design,"IEEE Design Test Comput., vol. 1, pp. 2139, Aug. 1984.
[2] H. Fleisher and L. I. Maissel, "An introduction to array logic,"IBM J. Res. Develop., vol. 19, pp. 98109, Mar. 1975.
[3] E. I. Muehldorf and T. W. Williams, "Optimized stuck fault test pattern generation for PLA macros," inDig. Semiconductor Test Symp., Cherry Hill, NJ, Oct. 2527, 1977, pp. 88101.
[4] D. L. Ostapko and S. J. Hong, "Fault analysis and test generation for programmable logic arrays,"IEEE Trans. Comput., vol. C28, pp. 617626, Sept. 1979.
[5] J. Smith, "Detection of faults in programmable logic arrays,"IEEE Trans. Comput., vol. C28, pp. 845853, Nov. 1979.
[6] P. Bose and J. A. Abraham, "Test generation for programmable logic arrays," inProc. 19th Design Automat. Conf., Las Vegas, NV, June 1982, pp. 574580.
[7] P. Bose, "Logical fault analysis and design for testability of programmable logic arrays," inProc. 23rd Annu. Allerton Conf., Monticello, Oct. 1985, pp. 158167.
[8] P. Bose, "Functional testing of programmable logic arrays," IBM Res. Rep. RC 10681, Oct. 1984.
[9] R. S. Wei and A. SangiovanniVincentelli, "PLATYPUS: A PLA test pattern generation tool,"IEEE Trans. Comput.Aided Design, vol. CAD5, pp. 633644, Oct. 1986.
[10] V. K. Agarwal, "Multiple fault detection in programmable logic arrays,"IEEE Trans. Comput., vol. C29, pp. 518522, June 1980.
[11] K. S. Ramanatha and N. N. Biswas, "A design for testability of undetectable crosspoint faults in programmable logic arrays,"IEEE Trans. Comput., vol. C32, pp. 551557, June 1983.
[12] S. M. Reddy and D. S. Ha, "A new approach to the design of testable PLA's,"IEEE Trans. Comput., vol. C36, pp. 201211, Feb. 1987.
[13] H. Fujiwara and K. Kinoshita, "A design of programmable logic arrays with universal test sets,"IEEE Trans. Comput., vol. C30, pp. 823828, Nov. 1981.
[14] J. P. Roth, W. G. Bouricius, and P. R. Schneider, "Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,"IEEE Trans. Electron. Comput., vol. EC16, pp. 567579, Oct, 1967.
[15] N. Ishiura, H. Yasuura, and S. Yajima, "Highspeed logic simulation on Vector processors,"IEEE Trans. Comput.Aided Design, vol. CAD6, May 1987.
[16] D. L. Ostapko, Z. Barzilai, and G. M. Silberman, "Fast fault simulation in a parallel processing environment," inProc. Int. Test Conf., Washington, DC, Sept. 1987.
[17] F. Darema and G. F. Pfister, "Multipurpose parallelism for VLSI CAD on the RP3,"IEEE Design Test Comput., vol. 4, pp. 1927, Oct. 1987.
[18] F. Daremaet al., "A singleprogrammultipledata computational model for EPEX Fortran," IBM Res. Rep. RC 11552, Yorktown Heights, NY, Oct. 1986.
[19] D. J. Kuck,The Structure of Computers and Computations, vol. 1. New York: Wiley, 1978.
[20] B. Liu and N. Strother, "Peak vector performance from VS Fortran," IBM Res. Rep. RC 12849, June 1987.
[21] P. Bose, "Heuristic, rulebased program transformations for enhanced vectorization," submitted for publication; available as IBM Res. Rep. RC 13472, Yorktown Heights, NY, Jan. 1988.
[22] K. Hwang, "Partitioned matrix algorithms for VLSI arithmetic systems,"IEEE Trans. Comput., vol. C31, pp. 12151224, Dec. 1982.
[23] R. M. Russel, "The CRAY1 computer system,"Commun. ACM, vol. 21, no. 1, pp. 6372, Jan. 1978.
[24] Several papers on the IBM 3090 system, architecture and performance,IBM Syst. J., vol. 25, pp. 482, 1986.
[25] G. F. Pfisteret al., "The RP3 Research Parallel Processor Prototype (RP3): Introduction and architecture," inProc. Int. Conf. Parallel Processing, Aug. 1985, pp. 764771.
[26] R. Galivanche and S. M. Reddy, "A parallel PLA minimization program," inProc. 24th ACM/IEEE Design Automat. Conf., 1987, pp. 600607.
[27] P. Bose, "Fast fault simulation and test generation for PLAs in a parallel processing environment," IBM Res. Rep. RC 13343, Dec. 1987.
[28] S. Winograd,Arithmetic Complexity of Computations. Philadelphia: SIAM Press, 1980; second printing 1986.