A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
Issue No.12 - December (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.9734
A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran a
parallel implementation; logic/fault simulation; VLSI; array logic; vector parallel; logic arrays; logic CAD; parallel processing.
P. Bose, "A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem", IEEE Transactions on Computers, vol.37, no. 12, pp. 1569-1577, December 1988, doi:10.1109/12.9734