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Timing Analysis Using Functional Analysis
October 1988 (vol. 37 no. 10)
pp. 1309-1314
The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it could be found that a long path is never activated. This results in more accurate delays. A comparison is made of three arrival time functions, A, B, and R. A is the arrival time as given by exhaustive simulation; B

[1] R. B. Hitchcock, Sr., G. L. Smith, and D. D. Cheng, "Timing analysis of computer hardware,"IBM J. Res. Develop., pp. 100-105, Jan. 1982.
[2] M. A. Breuer and A. D. Friedman,Diagnosis and Reliable Design of Digital Systems. Rockville, MD: Computer Science press, 1976.
[3] D. Brand, "Redundancy and DON'T CARES in logic synthesis,"IEEE Trans. Comput., vol. C-32, Oct. 1983.
[4] D. Brand and V. S. Iyengar, "Timing analysis using functional analysis,"IBM J. Res. Rep., RC 11768, Mar. 1986.
[5] J. A. Darringer, D. Brand, J. V. Gerbi, W. H. Joyner, Jr., and L. Trevillyan, "LSS: A system for production logic synthesis,"IBM J. Res. Develop., vol. 28, Sept. 1984.
[6] CMOS Macrocell Manual AR50-000001-20 B, LSI Inc.

Index Terms:
timing analysis; functional analysis; logic circuits; block-oriented algorithm; arrival time; logic circuits; logic design; logic testing.
Citation:
D. Brand, V.S. Iyengar, "Timing Analysis Using Functional Analysis," IEEE Transactions on Computers, vol. 37, no. 10, pp. 1309-1314, Oct. 1988, doi:10.1109/12.5996
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