Issue No.10 - October (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.5989
The authors present the design of self-checking sequential machines using standard memory elements, i.e. D, T, or JK flip-flops. The design approach involves cascading the three parts of a sequential machine, i.e. excitation, memory elements, and the output circuit. Parity is used to detect and transmit errors from one part to the next. The conditions for testing D, T, and JK flip-flops and for
error detection; error transmission; self-checking sequential machines; design; memory elements; flip-flops; excitation; flip-flops; sequential machines.
S. Dhawan, R.C. De Vries, "Design of Self-Checking Sequential Machines", IEEE Transactions on Computers, vol.37, no. 10, pp. 1280-1284, October 1988, doi:10.1109/12.5989