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On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
October 1988 (vol. 37 no. 10)
pp. 1273-1280
ASCII Text
x 
 
H.M. Shao, I.S. Reed, "On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays," IEEE Transactions on Computers, vol. 37, no. 10, pp. 1273-1280, October, 1988.
 
 
BibTex
x
 
@article{ 10.1109/12.5988,
author = {H.M. Shao and I.S. Reed},
title = {On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays},
journal ={IEEE Transactions on Computers},
volume = {37},
number = {10},
issn = {0018-9340},
year = {1988},
pages = {1273-1280},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.5988},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
IS - 10
SN - 0018-9340
SP1273
EP1280
EPD - 1273-1280
A1 - H.M. Shao,
A1 - I.S. Reed,
PY - 1988
KW - erasure correction; Euclid algorithm; VLSI design; pipeline Reed-Solomon decoder; systolic arrays; transform decoding technique; time-domain algorithm; multiplexing technique; cellular arrays; decoding; VLSI.
VL - 37
JA - IEEE Transactions on Computers
ER -
 
A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporate

[1] H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder,"IEEE Trans. Comput., vol. C-34, May 1985.
[2] R. P. Brent and H. T. Kung, "Systolic VLSI arrays for polynomial GCD computations," Dep. Comput. Sci., Carnegie-Melon Univ., Pittsburgh, PA, Rep., 1982.
[3] H. M. Shao, T. K. Truong, J. S. Hsu, L. J. Deutsch, and I. S. Reed, "A single chip VLSI Reed-Solomon decoder," Jet Propulsion Lab. TDA Progress Rep. 42-84, Oct.-Dec. 1985.
[4] I. S. Reed, T. K. Truong, and R. L. Miller, "Decoding of BCH and RS codes with errors and erasures using continued fractions,"Electron. Lett., July 1979.
[5] W. L. Eastman, private communication, MITRE Corp., Apr. 1986.
[6] R. J. McEliece,The Theory of Information and Coding. Reading, MA: Addison-Wesley, 1977.
[7] E. R. Berlekamp, "Bit-serial Reed-Solomon encoders,"IEEE Trans. Inform. Theory, vol. IT-28, pp. 869-874, Nov. 1982.

Index Terms:
erasure correction; Euclid algorithm; VLSI design; pipeline Reed-Solomon decoder; systolic arrays; transform decoding technique; time-domain algorithm; multiplexing technique; cellular arrays; decoding; VLSI.
Citation:
H.M. Shao, I.S. Reed, "On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays," IEEE Transactions on Computers, vol. 37, no. 10, pp. 1273-1280, Oct. 1988, doi:10.1109/12.5988
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