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Issue No.10 - October (1988 vol.37)
pp: 1273-1280
ABSTRACT
A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporate
INDEX TERMS
erasure correction; Euclid algorithm; VLSI design; pipeline Reed-Solomon decoder; systolic arrays; transform decoding technique; time-domain algorithm; multiplexing technique; cellular arrays; decoding; VLSI.
CITATION
H.M. Shao, I.S. Reed, "On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays", IEEE Transactions on Computers, vol.37, no. 10, pp. 1273-1280, October 1988, doi:10.1109/12.5988
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