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On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
October 1988 (vol. 37 no. 10)
pp. 1273-1280
A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporate

[1] H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder,"IEEE Trans. Comput., vol. C-34, May 1985.
[2] R. P. Brent and H. T. Kung, "Systolic VLSI arrays for polynomial GCD computations," Dep. Comput. Sci., Carnegie-Melon Univ., Pittsburgh, PA, Rep., 1982.
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[7] E. R. Berlekamp, "Bit-serial Reed-Solomon encoders,"IEEE Trans. Inform. Theory, vol. IT-28, pp. 869-874, Nov. 1982.

Index Terms:
erasure correction; Euclid algorithm; VLSI design; pipeline Reed-Solomon decoder; systolic arrays; transform decoding technique; time-domain algorithm; multiplexing technique; cellular arrays; decoding; VLSI.
Citation:
H.M. Shao, I.S. Reed, "On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays," IEEE Transactions on Computers, vol. 37, no. 10, pp. 1273-1280, Oct. 1988, doi:10.1109/12.5988
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