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V.S. Cherkassky, "Performance Evaluation of Nonrectangular Multistage Interconnection Networks," IEEE Transactions on Computers, vol. 37, no. 10, pp. 12691272, October, 1988.  
BibTex  x  
@article{ 10.1109/12.5987, author = {V.S. Cherkassky}, title = {Performance Evaluation of Nonrectangular Multistage Interconnection Networks}, journal ={IEEE Transactions on Computers}, volume = {37}, number = {10}, issn = {00189340}, year = {1988}, pages = {12691272}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.5987}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Performance Evaluation of Nonrectangular Multistage Interconnection Networks IS  10 SN  00189340 SP1269 EP1272 EPD  12691272 A1  V.S. Cherkassky, PY  1988 KW  performance evaluation; nonrectangular multistage interconnection networks; unbuffered packetswitching; closedform analytical expression; probability; multiprocessor interconnection networks; packet switching; performance evaluation. VL  37 JA  IEEE Transactions on Computers ER   
[1] T. Y. Feng, "A survey of interconnection networks,"Computer, pp. 1227, Dec. 1981.
[2] H. J. Siegel, R. H. McMillen, and P. T. Mueller, "A survey of interconnection methods for reconfigurable parallel processing systems," inAFIPS Conf. Proc., vol. 48, June 1979, pp. 529542.
[3] C. L. Wu and T. Y. Feng, "On a class of multistage interconnection networks,"IEEE Trans. Comput., vol. C29, pp. 694702, Aug. 1980.
[4] D. K. Pradhan and K. L. Kodandapani, "A uniform representation of single and multistage interconnection networks used in SIMD machines,"IEEE Trans. Comput., vol. C29, pp. 777790, Sept. 1980.
[5] D. P. Agrawal, "Graph theoretic analysis and design of multistage interconnection networks,"IEEE Trans. Comput., vol. C32, pp. 637648, July 1983.
[6] J. H. Patel, "Performance of processormemory interconnection for multiprocessors,"IEEE Trans. Comput., vol. C30, pp. 771780, Oct. 1981.
[7] D. M. Dias and J. R. Jump, "Analysis and simulation of buffered delta networks,"IEEE Trans. Comput., vol. C30, pp. 273282, Apr. 1981.
[8] N. J. Davis, IV and H. J. Siegel, "Performance studies of multiplepacket multistage cube networks and comparison to circuit switching," inProc. 1986 ICPP, pp. 108114.
[9] C. P. Kruskal and M. Snir, "The performance of multistage interconnection networks for multiprocessors,"IEEE Trans. Comput., vol. C32, pp. 10911098, Dec. 1983.
[10] L. R. Goke and G. J. Lipovski, "Banyan networks for partitioning multiprocessor systems," inProc. 1st Annu. Symp. Comput. Architecture, Dec. 1973, pp. 2128.
[11] U. V. Premkumar and J. C. Browne, "Resource allocation in rectangular SWbanyans," inProc. 9th Annu. Symp. Comput. Architecture, Apr. 1982, pp. 326333.
[12] L. N. Bhuyan and D. P. Agrawal, "Design and performance of generalized interconnection networks,"IEEE Trans. Comput., vol. C32, pp. 10811090, Dec. 1983.
[13] V. Premkumar, R. Kapur, M. Malek, G. J. Lipovski, and P. Horne, "Design and implementation of the banyan interconnection networks in TRAC,"Proc. NCC, vol. 249, pp. 643653, 1980.
[14] M. Lee and C.L. Wu, "Performance analysis of circuit switching baseline interconnection network," inProc. 11th Annu. Symp. Comput. Architecture, 1984, pp. 8290.
[15] S. Cheemalavagu and M. Malek, "Analysis and simulation of banyan interconnection networks with 2×2, 4×4 and 8×8 switching elements," inProc. RealTime Syst. Symp., Dec. 1982, pp. 8389.
[16] R. J. McMillen, G. B. Adams, and H. J. Siegel, "Performance and implementation of 4×4 switching nodes in an interconnection network for PASM," inProc. Int. Conf. Parallel Processing, Aug. 1981, pp. 229233.
[17] V. Cherkassky and M. Malek, "On permuting properties of regular rectangular SWbanyans,"IEEE Trans. Comput., vol. C34, pp. 542546, June 1985.