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Efficient Testing of Optimal Time Adders
September 1988 (vol. 37 no. 9)
pp. 1113-1121
Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log/sub 2/(n)-4 and 6 log/sub 2/(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of basic cells). The results are considered per

[1] M. S. Abadir and H. K. Reghbati, "Functional testing of semiconductor random access memories,"Comput. Surveys, vol. 15, no. 3, pp. 175-198, Sept. 1983.
[2] J. A. Abraham and D. D. Gajski, "Design of testable structures defined by simple loops,"IEEE Trans. Comput., vol. C-30, pp. 875- 883, 1981.
[3] B. Becker, "An easily testable optimal-time VLSI multiplier," ActaInformatica, vol. 24, pp. 363-380, 1987.
[4] B. Becker and H. Soukup, "CMOS stuck-open self-test for an optimal-time VLSI-multiplier," T.R., 04/1986, SFB 124, Saarbrücken 1986; also inMicroprocessing and Microprogramming, Euromicro J.Amsterdam, The Netherlands: North Holland, 1986, vol. 20, 1987, pp. 153-157.
[5] B. Becker, G. Hotz, R. Kolla, and P. Molitor, "Ein CAD-System zum Entwurf integrierter Schaltungen," T.R., 16/1984, SFB 124, Saarbrücken.
[6] R. P. Brent and H. T. Kung, "A regular layout for parallel adders,"IEEE Trans. Comput., vol. C-31, pp. 260-264, 1982.
[7] M. A. Breuer, Ed.,Diagnosis and Reliable Design of Digital Systems. Woodland Hills, CA: Computer Science Press, 1976.
[8] W. Daehn and J. Mucha, "A hardware approach to self-testing of large PLA's,"IEEE Trans. Circuits Syst., vol. CAS-28, p. 1033, 1981.
[9] J. Ferguson and J. P. Shen, "The design of two easily-testable VLSI array multipliers," inProc. 6th Symp. Comput. Arithmetic, June 20-22, 1983, Aarhus, Denmark, IEEE Catalog no. 83CH1892-9.
[10] A. D. Friedman, "Easily testable iterative systems,"IEEE Trans. Comput., vol. C-22, pp. 1061-1064, 1973.
[11] W. H. Kautz, "Testing for faults in cellular logic arrays," inProc. 8th Symp. Switch. Automat. Theory, 1967, pp. 161-174.
[12] R. K. Montoye and J. A. Abraham, "Built-in tests for abitrarily structured VLSI carry look-ahead adders," inProc. IFIP, 1983, pp. 361-371.
[13] J. Sklansky, "Conditional-sum addition logic,"IRE Trans. Electron. Comput., vol. EC-9, pp. 226-231, 1960.
[14] J. E. Smith, "Detection of faults in PLA's,"IEEE Trans. Comput., vol. C-28, p. 845, 1979.
[15] J. Vuillemin and L. Guibas, "On fast binary addition in MOS technologies," inProc. ICCC, 1982, pp. 147-150.
[16] W. K. Luk and J. Vuillemin, "Recursive implementation of optimal time VLSI integer multipliers," inProc. IFIP, 1983, pp. 155-168.

Index Terms:
optimal time adders; carry look-ahead adder; conditional sum adder; VLSI chip; adders; integrated logic circuits; logic testing; VLSI.
B. Becker, "Efficient Testing of Optimal Time Adders," IEEE Transactions on Computers, vol. 37, no. 9, pp. 1113-1121, Sept. 1988, doi:10.1109/12.2262
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