Issue No.09 - September (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2262
Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log/sub 2/(n)-4 and 6 log/sub 2/(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of basic cells). The results are considered per
optimal time adders; carry look-ahead adder; conditional sum adder; VLSI chip; adders; integrated logic circuits; logic testing; VLSI.
B. Becker, "Efficient Testing of Optimal Time Adders", IEEE Transactions on Computers, vol.37, no. 9, pp. 1113-1121, September 1988, doi:10.1109/12.2262