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B. Becker, "Efficient Testing of Optimal Time Adders," IEEE Transactions on Computers, vol. 37, no. 9, pp. 11131121, September, 1988.  
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@article{ 10.1109/12.2262, author = {B. Becker}, title = {Efficient Testing of Optimal Time Adders}, journal ={IEEE Transactions on Computers}, volume = {37}, number = {9}, issn = {00189340}, year = {1988}, pages = {11131121}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.2262}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Efficient Testing of Optimal Time Adders IS  9 SN  00189340 SP1113 EP1121 EPD  11131121 A1  B. Becker, PY  1988 KW  optimal time adders; carry lookahead adder; conditional sum adder; VLSI chip; adders; integrated logic circuits; logic testing; VLSI. VL  37 JA  IEEE Transactions on Computers ER   
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