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Test Scheduling and Control for VLSI Built-in Self-Test
September 1988 (vol. 37 no. 9)
pp. 1099-1109
The test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for definin

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Index Terms:
VLSI; built-in self-test; test scheduling; BIST; hierarchical model; test resource sharing; suboptimum algorithms; equal length test; unequal length test; algorithm performance; automatic testing; integrated circuit testing; scheduling; VLSI.
Citation:
G.L. Craig, C.R. Kine, K.K. Saluja, "Test Scheduling and Control for VLSI Built-in Self-Test," IEEE Transactions on Computers, vol. 37, no. 9, pp. 1099-1109, Sept. 1988, doi:10.1109/12.2260
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