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Modular Error Detection for Bit-Serial Multiplication
September 1988 (vol. 37 no. 9)
pp. 1043-1052
Special-purpose architectures have been proposed to provide high processing rates for signal processing applications. These architectures use highly concurrent structures on VLSI circuits to achieve billions of multiply/add operations per second. Both serial-parallel and fully bit-serial multiplier elements have been proposed for highly concurrent signal processing arrays. Error detection can b

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Index Terms:
bit-serial multiplication; VLSI circuits; serial-parallel; multiplier elements; signal processing arrays; arithmetic codes; residue; error detection; computer simulation; error detection codes; multiplying circuits; VLSI.
T.J. Brosnan, N.R. Strader, II, "Modular Error Detection for Bit-Serial Multiplication," IEEE Transactions on Computers, vol. 37, no. 9, pp. 1043-1052, Sept. 1988, doi:10.1109/12.2255
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