This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Modular Error Detection for Bit-Serial Multiplication
September 1988 (vol. 37 no. 9)
pp. 1043-1052
Special-purpose architectures have been proposed to provide high processing rates for signal processing applications. These architectures use highly concurrent structures on VLSI circuits to achieve billions of multiply/add operations per second. Both serial-parallel and fully bit-serial multiplier elements have been proposed for highly concurrent signal processing arrays. Error detection can b

[1] D. F. Barbe,Very Large Scale Integration (VLSI). New York: Springer-Verlag, 1982.
[2] H. T. Kung, "Let's design algorithms for VLSI systems," inProc. Caltech Conf. VLSI, Jan. 1979, pp. 65-90.
[3] R. F. Lyon, "Two's complement pipeline multipliers,"IEEE Trans. Commun., vol. COM-24, no. 4, pp. 418-425, Apr. 1976.
[4] N. R. Strader and V. T. Rhyne, "A canonical bit-sequential multiplier,"IEEE Trans. Comput., Aug. 1982.
[5] I. N. Chen and R. Willoner, "AnO(n)parallel multiplier with bit-sequential input and output,"IEEE Trans. Comput., vol. C-28, pp. 721-727, Oct. 1979.
[6] T. R. N. Rao,Error Coding for Arithmetic Processors. New York: Academic, 1974.
[7] N. R. Strader, "VLSI bit-sequential architectures for digital signal processing," inICASSP 83 Proc., vol. 3, Apr. 1983.
[8] M. W. Sievers and A. Avizienis, "Analysis of a class of totally self-checking functions implemented in a MOS LSI general logic structure," inProc. FTCS-10, 1980, pp. 256-261.
[9] O. Tasar and V. Tasar, "A study of intermittent faults in digital computers," inAFIPS Conf. Proc., vol. 46, 1979, pp. 807-811.
[10] T. Mangir and A. Avizienis, "Failure modes for VLSI and their effect on chip design," inProc. IEEE 1st Int. Conf. Circuits Comput., Oct. 1980, pp. 685-688.
[11] L. G. Gallace, H. L. Pujol, and G. L. Schnable, "CMOS reliability," inProc. 27th Electron. Components Conf., May 1977, pp. 496-512.
[12] J. Galiay, Y. Crouzet, and M. Vergniault, "Physical versus logical fault models in MOS LSI circuits, impact on their testability," inProc. FTCS-9, 1979, pp. 195-202.
[13] S. Lin and D. J. Costello, Jr.,Error Control Coding: Fundamentals and Applications. Englewood Cliffs, NJ: Prentice-Hall, 1983.
[14] J. F. Wakerly,Error Detecting Codes, Self-Checking Circuits, and Applications. New York: Elsevier North-Holland, 1978.
[15] W. W. Peterson,Error-Correcting Codes. Cambridge, MA: MIT Press, 1961.
[16] F. F. Sellers, M.-Y. Hsiao, and L. W. Bearnson,Error Detecting Logic for Digital Computers. New York: McGraw-Hill, 1968.
[17] A. Avizienis, "Arithmetic error codes: Cost and effectiveness studies for application in digital system design,"IEEE Trans. Comput., vol. C-20, pp. 1322-1331, Nov. 1971.
[18] A. Avizienis, "A set of algorithms for a diagnosable arithmetic unit," JPL Tech. Rep. 32-546, Mar. 1964.
[19] J. B. Clary and R. A. Sacane, "Self-testing computers,"Computer, vol. 13, Oct. 1979.
[20] D. A. Anderson and G. Metze, "Design of totally self-checking check circuits form-out-of-ncodes,"IEEE Trans. Comput., vol. C-22, pp. 263-269, Mar. 1973.
[21] Y. Tamir and C. H. Séquin, "Design and application of self-testing comparators implemented with MOS PLA's,"IEEE Trans. Comput., vol. C-33, pp. 493-506, June 1984.
[22] J. L. A. Hughes, E. J. McCluskey, and D. J. Lu, "Design of totally self-checking comparators with an arbitrary number of inputs,"IEEE Trans. Comput., vol. C-33, pp. 546-550, June 1984.
[23] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.

Index Terms:
bit-serial multiplication; VLSI circuits; serial-parallel; multiplier elements; signal processing arrays; arithmetic codes; residue; error detection; computer simulation; error detection codes; multiplying circuits; VLSI.
Citation:
T.J. Brosnan, N.R. Strader, II, "Modular Error Detection for Bit-Serial Multiplication," IEEE Transactions on Computers, vol. 37, no. 9, pp. 1043-1052, Sept. 1988, doi:10.1109/12.2255
Usage of this product signifies your acceptance of the Terms of Use.