Issue No.09 - September (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2254
Linear sum codes (LSCs) form a class of error control codes designed to provide on-chip error correction to semiconductor random access memories (RAMs). They use the natural addressing scheme found on RAMs to form and access codewords with a minimum of overhead. The authors formally define linear sum codes and examine some of their characteristics. Specifically, they examine their minimum dista
linear sum codes; random access memories; LSCs; error control codes; on-chip error correction; semiconductor random access memories; error correcting; error correction codes; random-access storage.
T. Fuja, C. Heegard, R. Goodman, "Linear Sum Codes for Random Access Memories", IEEE Transactions on Computers, vol.37, no. 9, pp. 1030-1042, September 1988, doi:10.1109/12.2254