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Q-Modules: Internally Clocked Delay-Insensitive Modules
September 1988 (vol. 37 no. 9)
pp. 1005-1018
Q-modules are internally clocked modules that can be used to satisfy delay-insensitive specifications. A single delay element is required with a one-sided bound that its value be greater than the maximum delay of the combination logic. Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, an

[1] T. J. Chaney and C. E. Molnar, "Anomalous behavior of synchronizers and arbiter circuits,"IEEE Trans. Comput., vol. C-22, pp. 421-422, Apr. 1973.
[2] T. J. Chaney, "Measured flip-flop responses to marginal triggering,"IEEE Trans. Comput., vol. C-32, pp. 1207-1209, Dec. 1983.
[3] D. M. Chapiro, "Globally-asynchronous locally-synchronous systems," STAN-CS-84-1026, Dep. Comput. Sci., Stanford Univ., Stanford, CA 94305, Oct. 1984.
[4] W. A. Clark and C. E. Molnar, "Macromodular computer systems," inComputers in Biomedical Research, Vol. IV, B. Waxman and R. Stacey, Eds. New York: Academic, 1974, pp. 45-85.
[5] M. Golubitsky and D. G. Schaeffer,Singularities and Groups in Bifurcation Theory. New York: Springer-Verlag, 1985.
[6] Z. Kohavi,Switching and Finite Automata Theory, 2nd ed. New York: McGraw-Hill, 1978.
[7] W. Lim and J. R. Cox, Jr., "Clocks and the performance of synchronizers,"Proc. IEE, vol. 130, pp. 57-64, Mar. 1983.
[8] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[9] R. E. Miller,Switching Theory: Vol. II: Sequential Circuits and Machines. New York: NY, Wiley, 1965.
[10] C. E. Molnar, T. P. Fang and F. U. Rosenberger, "Synthesis of delay-insensitive modules," inProc. 1985 Chapel Hill Conf. VLSI, Chapel Hill, NC, May 15-17, 1985, pp. 67-86.
[11] M. Pechoucek, "Anomalous response times of input synchronizers,"IEEE Trans. Comput., vol. C-25, pp. 133-139, Feb. 1976.
[12] M. Rem, J. L. A. Snepscheut, and J. T. Udding, "Trace theory and the definition of hierarchical components," inProc. Third Caltech Conf. Very Large Scale Integration, Pasadena, CA, Jan. 1983.
[13] C. L. Seitz, "System timing," inIntroduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison, Wesley, 1980, ch. 7.
[14] M. J. Stucki, S. M. Ornstein, and W. A. Clark, "Logical design of macromodules,"AFIPS Proc., vol. 30,Spring Joint Comput. Conf., 1967, pp. 357-364.
[15] M. J. Stucki and J. R. Cox, Jr., "Synchronization strategies," inProc. Caltech Conf. VLSI, Pasadena, CA, Jan. 1979, pp. 375-393.
[16] J. T. Udding, "A formal model for defining and classifying delayinsensitive circuits and systems,"Distributed Comput., vol. 1, pp. 197-204, 1986.
[17] S. H. Unger,Asynchronous Sequential Switching Theory. New York: Wiley, 1969.
[18] T. W. Williams and K. P. Parker, "Design for testability--A survey,"IEEE Trans. Comput., vol. C-31, pp. 2-15, Jan. 1982; also inProc. IEEE, vol. 71, pp. 98-112, Jan. 1983.

Index Terms:
testability; Q-modules; internally clocked; delay-insensitive; QSYN; CMOS realization; testing; asynchronous sequential logic; CMOS integrated circuits; integrated logic circuits; logic design; logic testing; sequential circuits.
Citation:
F.U. Rosenberger, C.E. Molnar, T.J. Chaney, T.-P. Fang, "Q-Modules: Internally Clocked Delay-Insensitive Modules," IEEE Transactions on Computers, vol. 37, no. 9, pp. 1005-1018, Sept. 1988, doi:10.1109/12.2252
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