This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fault Tolerance in a Systolic Residue Arithmetic Processor Array
July 1988 (vol. 37 no. 7)
pp. 886-890
ASCII Text
x 
 
R.J. Cosentino, "Fault Tolerance in a Systolic Residue Arithmetic Processor Array," IEEE Transactions on Computers, vol. 37, no. 7, pp. 886-890, July, 1988.
 
 
BibTex
x
 
@article{ 10.1109/12.2239,
author = {R.J. Cosentino},
title = {Fault Tolerance in a Systolic Residue Arithmetic Processor Array},
journal ={IEEE Transactions on Computers},
volume = {37},
number = {7},
issn = {0018-9340},
year = {1988},
pages = {886-890},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.2239},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Fault Tolerance in a Systolic Residue Arithmetic Processor Array
IS - 7
SN - 0018-9340
SP886
EP890
EPD - 886-890
A1 - R.J. Cosentino,
PY - 1988
KW - fault tolerance; systolic residue arithmetic processor array; redundancy; VLSI systems; ultrahigh-reliability switches; finite-impulse-response filter; digital arithmetic; fault tolerant computing.
VL - 37
JA - IEEE Transactions on Computers
ER -
 
The regularity of systolic arrays and the potential for redundancy in residue number systems are used to provide fault tolerance in VLSI systems. The fault tolerance is concurrent with normal circuit operation and allows a continuous flow of correct data when a fault occurs. There is no interruption of valid data flow while the circuits are reconfigured. The technique also obviates the need for

[1] H. T. Kung, "Why systolic architectures?,"IEEE Computer, pp. 37- 42, Jan. 1982.
[2] F. J. Taylor, "Residue arithmetic: A tutorial with examples,"IEEE Computer, pp. 50-62, May 1984.
[3] R. D. Haggarty, B. L. Johnson, and E. A. Palo, "A revolutionary design method for VLSI signal processing," inAGARD Avionics Panel Symp. Rec., May 1985.
[4] D. R. Bungard, S. Dhar, T. M. Hopkinson, and P. V. McDonough, "Adaptive quadrature processing using a VLSI-based RNS-systolic FIR filter," in1986 Govern. Microcircuit Appl. Conf. (GOMAC) Dig., San Diego, CA, Nov. 11-13, 1986, pp. 419-422.
[5] F. T. Leighton and C. E. Leiserson, "Wafer-scale integration of systolic arrays,"IEEE Trans. Comput., vol. C-34, pp. 448-461, May 1985.
[6] H. T. Kung, "Wafer-scale integration and two-level pipelined implementations of systolic arrays,"J. Parallel Distributed Processing, vol. 1, Aug. 1984.
[7] T. E. Mangir, "Source of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part II-Restructurable interconnects for RVLSI and WSI,"Proc. IEEE, vol. 72, pp. 1687-1694, Dec. 1984.
[8] M. Sami and R. Stefanelli, "Reconfigurable architectures for VLSI processing arrays,"Proc. IEEE, vol. 74, pp. 712-722, May 1986.
[9] J.-Y. Jou and J. A. Abraham, "Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures,"Proc. IEEE, vol. 74, pp. 732-741, May 1986.
[10] K.-H. Huang and J. A. Abraham, "Algorithm-based fault tolerance for matrix operations,"IEEE Trans. Comput., vol. C-33, pp. 518-528, June 1984.
[11] N. S. Szabo and R. I. Tanaka,Residue Arithmetic and its Applications to Computer Technology. New York: McGraw-Hill, 1967.
[12] R. W. Watson, "Error detection and correction and other residueinteracting operations in a redundant residue number system," Ph.D. dissertation, Dep. Elec. Eng., Univ. California, Berkeley, Jan. 6, 1965.
[13] R. W. Watson and C. W. Hastings, "Self-checked computation using residue arithmetic,"Proc. IEEE, vol. 54, pp. 1920-1931, Dec. 1966.
[14] D. Mandelbaum, "Error correction in residue arithmetic,"IEEE Trans. Comput., vol. C-21, pp. 538-545, June 1972.
[15] F. Barsi and P. Maestrini, "Error correcting properties of redundant residue number systems,"IEEE Trans. Comput., vol. C-22, pp. 307-315, Mar. 1973.

Index Terms:
fault tolerance; systolic residue arithmetic processor array; redundancy; VLSI systems; ultrahigh-reliability switches; finite-impulse-response filter; digital arithmetic; fault tolerant computing.
Citation:
R.J. Cosentino, "Fault Tolerance in a Systolic Residue Arithmetic Processor Array," IEEE Transactions on Computers, vol. 37, no. 7, pp. 886-890, July 1988, doi:10.1109/12.2239
Usage of this product signifies your acceptance of the Terms of Use.