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Fault Tolerance in a Systolic Residue Arithmetic Processor Array
July 1988 (vol. 37 no. 7)
pp. 886-890
The regularity of systolic arrays and the potential for redundancy in residue number systems are used to provide fault tolerance in VLSI systems. The fault tolerance is concurrent with normal circuit operation and allows a continuous flow of correct data when a fault occurs. There is no interruption of valid data flow while the circuits are reconfigured. The technique also obviates the need for

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Index Terms:
fault tolerance; systolic residue arithmetic processor array; redundancy; VLSI systems; ultrahigh-reliability switches; finite-impulse-response filter; digital arithmetic; fault tolerant computing.
Citation:
R.J. Cosentino, "Fault Tolerance in a Systolic Residue Arithmetic Processor Array," IEEE Transactions on Computers, vol. 37, no. 7, pp. 886-890, July 1988, doi:10.1109/12.2239
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