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Communication Performance in Multiple-Bus Systems
July 1988 (vol. 37 no. 7)
pp. 848-853
A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is sim

[1] S. Hoener and W. Roehder, "Efficiency of a multi-micro-processor system with time shared buses,"EUROMICRO, pp. 35-42, 1977.
[2] D. P. Bhandarkar, "Analysis of memory interference in multiprocessors,"IEEE Trans. Comput., vol. C-24, pp. 897-908, Sept. 1975.
[3] J. H. Patel, "Performance of processor memory interconnections for multiprocessors,"IEEE Trans. Comput., vol. C-30, pp. 771-780, Oct. 1981.
[4] T. Lang, M. Valero, and I. Algre, "Bandwidth of crossbar and multiple-bus connections for multiprocessors,"IEEE Trans. Comput., vol. C-31, pp. 1227-1234, Dec. 1982.
[5] L. N. Bhuyan, "A combinational analysis of multibus multiprocessors," inProc. '84 Int. Conf. Parallel Processing, 1984, pp. 225- 227.
[6] T. N. Mudgeet al., "Analysis of multiple bus interconnection networks," inProc. '84 Int. Conf. Parallel Processing, 1984, pp. 228-232.
[7] M. A. Marsan and M. Gerla, "Markov models for multiple bus multiprocessor systems,"IEEE Trans. Comput., vol. C-31, pp. 239- 248, Mar. 1982.
[8] K. B. Iraniet al., "A closed-form solution for the performance analysis of multiple-bus multiprocessor systems,"IEEE Trans. Comput., vol. C-32, pp, 1004-1012, Nov. 1984.
[9] J. H. Patel, "Analysis of multiprocessors with private cache memories,"IEEE Trans. Comput., vol. C-31, pp. 296-304, Apr. 1982.
[10] C. Y. Hitchcosk III and H. M. Brinkley Sprunt, "Analyzing multiple register sets," inProc. 12th Annu. Int. Symp. Comput. Architecture, 1985, pp. 55-63.
[11] A. Gottliebet al., "The NYU ultracomputer-Designing a MIMD shared memory parallel computer,"IEEE Trans. Comput., vol. C- 32, pp. 175-189, Feb. 1983.
[12] A. J. Smith, "Sequential program prefetching in memory hierarchies,"IEEE Computer, vol. 11, pp. 7-21, Dec. 1978.
[13] P. Heidelberger and S. S. Lavenberg, "Computer performance evaluation methodology,"IEEE Trans. Comput., vol. C-33, pp. 1195-1220, Dec. 1984.
[14] E. D. Lazawskaet al., Quantitative System Performance--Computer System Analysis Using Queueing Network Models. Englewood Cliffs, NJ: Prentice-Hall, 1984.

Index Terms:
communication performance; multiple bus interconnection networks; queueing model; asynchronous multiprocessor systems; closed-form solution; memory modules; multiprocessor interconnection networks; performance evaluation; queueing theory.
Q. Yang, S.G. Zaky, "Communication Performance in Multiple-Bus Systems," IEEE Transactions on Computers, vol. 37, no. 7, pp. 848-853, July 1988, doi:10.1109/12.2230
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