Issue No.07 - July (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2229
An algebraic methodology for comparing switch-level circuits with higher-level specifications is presented. Switch-level networks, 'user' behavior, and input constraints are modeled as asynchronous machines. The model is based on the algebraic theory of characteristic functions (CF). An asynchronous automation is represented by a pair of CFs, called a dynamic CF (DCF): the first CF describes th
machine composition; logic testing; algebraic model; asynchronous circuits verification; switch-level circuits; asynchronous machines; asynchronous automation; Boolean algebra; Boolean inequalities; Boolean functions; logic testing; program verification.
C. Berthet, E. Cerny, "An Algebraic Model for Asynchronous Circuits Verification", IEEE Transactions on Computers, vol.37, no. 7, pp. 835-847, July 1988, doi:10.1109/12.2229