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C. Berthet, E. Cerny, "An Algebraic Model for Asynchronous Circuits Verification," IEEE Transactions on Computers, vol. 37, no. 7, pp. 835847, July, 1988.  
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@article{ 10.1109/12.2229, author = {C. Berthet and E. Cerny}, title = {An Algebraic Model for Asynchronous Circuits Verification}, journal ={IEEE Transactions on Computers}, volume = {37}, number = {7}, issn = {00189340}, year = {1988}, pages = {835847}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.2229}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  An Algebraic Model for Asynchronous Circuits Verification IS  7 SN  00189340 SP835 EP847 EPD  835847 A1  C. Berthet, A1  E. Cerny, PY  1988 KW  machine composition; logic testing; algebraic model; asynchronous circuits verification; switchlevel circuits; asynchronous machines; asynchronous automation; Boolean algebra; Boolean inequalities; Boolean functions; logic testing; program verification. VL  37 JA  IEEE Transactions on Computers ER   
[1] Barrow, H.G., "Verify: A Program for Proving Correctness of Digital Hardware Designs,"Artificial Intelligence, Vol. 24, 1984, pp. 437491.
[2] B. Beizer, "Towards a new theory of sequential switching networks,"IEEE Trans. Comput., vol. C19, pp. 939956, Oct. 1970.
[3] G. Bochmann, "Hardware specifications with temporal logic: An example,"IEEE Trans. Comput., vol. C31, no. 3, 1982.
[4] R. E. Bryant, "A switchlevel model and simulator for MOS digital systems,"IEEE Trans. Comput., vol. C33, no. 2, 1984.
[5] R. E. Bryant, "Symbolic verification of MOS circuits," inProc. Chapel Hill Conf. VLSI, 1985.
[6] J. A. Brzozowski and M. Yoeli, "On a ternary model of gate networks,"IEEE Trans. Comput., vol. C28, no. 3, pp. 178184, 1979.
[7] E. Cerny, "An approach to unified methodology of combinational switching circuits,"IEEE Trans. Comput., vol. C26, no. 8, 1977.
[8] E. Cerny, "Controllability and fault observability in modular combinational circuits,"IEEE Trans. Comput., vol. C27, no. 10, 1978.
[9] E. Cerny, "Characteristic functions in multivalued logic systems,"Digital Processes, vol. 6, pp. 167174, 1980.
[10] E. Cerny and J. Gecsei, "Simulation of MOS circuits by decision diagrams,"IEEE Trans. ComputerAided Design, vol. CAD4, pp. 685693, Oct. 1985.
[11] D. L. Dill and E. M. Clarke, "Automatic verification of asynchronous circuits using temporal logic," inProc. Chapel Hill Conf. VLSI, 1985.
[12] M. Gordon, "A model of register transfert systems with applications to microcode and VLSI correctness," Comput. Sci. Rep. CSR8281, Univ. Edinburgh, 1981.
[13] J. P. Hayes, "A unified switching theory with applications to VLSI design,"Proc. IEEE, vol. 70, no. 10, pp. 11401151, 1982.
[14] R. M. Keller, "Towards a theory of universal speedindependent modules,"IEEE Trans. Comput., vol. C23, no. 1, 1974.
[15] Z. Kohavi,Switching and Finite Automata Theory. New York: McGrawHill, 1978.
[16] S. M. Leinwand, "Automatic design verification and test generation for digital systems," Ph.D. dissertation, Weizmann Instit. Sci., Rehovot, 1980.
[17] L. R. Marino, "General theory of metastable operation,"IEEE Trans. Comput., vol. C30, no. 2, 1981.
[18] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: AddisonWesley, 1980, pp. 150152.
[19] R. E. Miller,Switching Theory. New York: Wiley, 1965.
[20] G. J. Milne, "A model for hardware description and verification," inProc. 21st Design Automat. Conf., 1984.
[21] B. Mishra and E. M. Clarke, "Automatic and hierarchical verification of asynchronous circuits using temporal logic," Tech. Rep. CMUCS 83155, CarnegieMellon Univ., Pittsburgh, PA, 1983.
[22] B. Moszkowski, "A temporal logic for multilevel reasoning about hardware,"IEEE Computer, no. 2, 1985.
[23] V. Pitchumani and E. P. Stabler, "An inductive assertion method for register transfer level design verification,"IEEE Trans. Comput., vol. C32, no. 12, 1983.
[24] S. Rudeanu,Boolean Functions and Equations. Amsterdam, The Netherlands: NorthHolland, 1974.
[25] R. Shostack, "Formal verification of circuit design," inProc. VI Int. Conf. Hardware Description Languages, IFIP, 1983.
[26] S. Unger,Asynchronous Sequential Switching Circuits, New York: WileyInterscience, 1969.
[27] T. J. Wagner, "Hardware verification," Ph.D. dissertation, STANCS77632, Stanford Univ., 1977.
[28] Wojcik, A.S., "A Formal Design Verification System Based on an Automated Reasoning System,"ACM IEEE 21st Design Automation Conf., July 1984, pp. 641647.
[29] L. Wos, R. Overbeek, E. Lusk, and J. Boyle,Automated Reasoning: Introduction and Applications. Englewood Cliffs, NJ: PrenticeHall, 1974.