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Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
July 1988 (vol. 37 no. 7)
pp. 807-814
A method is proposed that is based on the partitioning of the input code variables into two sections, each section representing the binary form of a number Z/sub 1/ and Z/sub 2/, respectively. For a code with check base A=2/sup m/-1, two m-bit end-around carry adder trees calculate the modulo m residue of Z/sub 1/ and Z/sub 2/, while a totally self-checking (TSC) translator maps the output of t

[1] A. Avizienis, "Arithmetic error codes: Cost and effectiveness studies for application in digital system design,"IEEE Trans. Comput., vol. C-20, pp. 1322-1331, Nov. 1971.
[2] T. R. N. Rao,Error Coding for Arithmetic Processors. New York: Academic, 1974.
[3] W. W. Peterson, "On checking an adder,"IBM J. Res. Develop., vol. 2, pp. 166-168, Apr. 1958.
[4] J. F. Wakerly, "Detection of unidirectional multiple errors using low-cost arithmetic codes,"IEEE Trans. Comput., vol. C-24, pp. 210- 212, Feb. 1975.
[5] B. Parhami and A. Avizienis, "Detection of storage errors in mass memories using low-cost arithmetic error codes,"IEEE Trans. Comput., vol. C-27, pp. 302-308, Apr. 1978.
[6] J. Wakerly,Error Detecting Codes Self-Checking Circuits and Applications. Amsterdam, The Netherlands: Elsevier North-Holland, 1978.
[7] H. L. Garner, "Error codes for arithmetic operations,"IEEE Trans. Electron. Comput., vol. EC-15, pp. 763-770, Oct. 1966.
[8] D. T. Brown, "Error detecting and correcting binary codes for arithmetic operations,"IRE Trans. Electron. Comput., vol. EC-9, pp. 333-337, Sept. 1960.
[9] W. C. Carter and P. R. Schneider, "Design of dynamically checked computers," inProc. IFIP Congress, 1968, vol. 2, pp. 878-883.
[10] D. A. Anderson, "Design of selfchecking digital networks using coding techniques," Univ. Illinois Coordinated Sci. Lab., Urbana, IL, Tech. Rep. R-527, Sept. 1971.
[11] D. A. Anderson and G. Metze, "Design of totally self-checking check circuits form-out-of-ncodes,"IEEE Trans. Comput., vol. C-12, pp. 263-269, Mar. 1973.
[12] N. Gaitanis, "Totally self-checking checkers for low-cost arithmetic codes,"IEEE Trans. Comput., vol. C-34, pp. 596-601, July 1985.
[13] J. L. A. Hughes, E. J. McCluskey, and D. J. Lu, "Design of totally self-checking comparators with an arbitrary number of inputs," inProc. 13th Int. Symp. Fault-Tolerant Comput., Milan, Italy, June 1983. pp. 169-172.
[14] J. L. A. Hughes, E. J. McCluskey, and D. J. Lu, "Design of totally self-checking comparators with an arbitrary number of inputs," Cent. Reliable Comput., Stanford Univ., Stanford, CA, Tech. Rep. 83-18, Nov. 1983.
[15] M. J. Ashjaee and S. M. Reddy, "On totally self-checking checkers for separable codes,"IEEE Trans. Comput., vol. C-26, pp. 737-744, Aug. 1977.
[16] J. F. Wakerly, "One's complement adder eliminates unwanted zero,"Electronics, pp. 103-105, Feb. 5, 1976.
[17] J. Khakbaz, "Totally self-checking checker for l-out-of-ncode using two-rail codes,"IEEE Trans. Comput., vol. C-31, pp. 677-681, July 1982.
[18] F. F. Sellers, M. Y. Hsiao, and L. W. Beamson,Error Detecting Logic for Digital Computers. New York: McGraw-Hill, 1968.
[19] G. G. Langdon, Jr. and C. K. Tang, "Concurrent error detection for group look-ahead binary adders,"IBM J. Res. Develop., pp. 563- 573, Sept. 1970.
[20] S. L. Wang and A. Avizienis, "The design of totally self checking circuits using programmable logic arrays," inProc. FTCS 9, June 1979, pp. 173-180.
[21] Y. Tamir and C. H. Sequin, "Design and application of self-testing comparators implemented with MOS PLA's,"IEEE Trans. Comput., vol. C-33, pp. 493-506, June 1984.
[22] T. G. Gaddes, "An error-detecting binary adder: A hardware-shared implementation,"IEEE Trans. Comput., vol. C-19, pp. 34-38, Jan. 1970.
[23] Texas Instruments,The TTL Data Book for Design Engineers, 2nd ed., Texas Instruments, Dallas, TX, 1976.
[24] M. A. Breuer and A. D. Friedman,Diagnosis and Reliable Design of Digital Systems. Marshfield, MA: Pitman, 1977.
[25] D. Nikolos, A. M. Paschalis, and G. Philokyprou, "Efficient design of totally self-checking checkers for all separate low-cost arithmetic codes," inProc. First Euro. Workshop Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, Aug. 31-Sept. 3, 1986.

Index Terms:
totally self-checking checkers; low-cost arithmetic codes; partitioning; trees; gate levels; reliability; error detection codes; fault tolerant computing.
D. Nikolos, A.M. Paschalis, G. Philokyprou, "Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes," IEEE Transactions on Computers, vol. 37, no. 7, pp. 807-814, July 1988, doi:10.1109/12.2226
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