Issue No.06 - June (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.2216
A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal.
bit-serial systolic multiplier; linear systolic array; cellular arrays; logic design; VLSI.
B.B. Zhou, "A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)", IEEE Transactions on Computers, vol.37, no. 6, pp. 749-751, June 1988, doi:10.1109/12.2216