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A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
June 1988 (vol. 37 no. 6)
pp. 749-751
A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal.

[1] H. T. Kung, "Why systolic architectures?,"IEEE Computer, vol. 15, pp. 37-46, Jan. 1982.
[2] F. J. Macwilliams and N. J. Sloane,The Theory of Error-Correcting Codes. Amsterdam: North-Holland, 1977.
[3] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[4] C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, and I. S. Reed, "VLSI architecture for computing multiplications and inverses in GF(2m),"IEEE Trans. Comput., vol. C-34, pp. 709-716, Aug. 1985.
[5] C.-S. Yeh, I. S. Reed, and T. K. Truong, "Systolic multipliers for finite fieldGF(2m),"IEEE Trans. Comput., vol. C-33, pp. 357-360, Apr. 1984.

Index Terms:
bit-serial systolic multiplier; linear systolic array; cellular arrays; logic design; VLSI.
B.B. Zhou, "A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)," IEEE Transactions on Computers, vol. 37, no. 6, pp. 749-751, June 1988, doi:10.1109/12.2216
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