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A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
June 1988 (vol. 37 no. 6)
pp. 735-739
Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so t

[1] E. R. Berlekamp, "Bit-serial Reed-Solomon encoders,"IEEE Trans. Inform. Theory, vol. IT-28, pp. 869-874, Nov. 1982.
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[3] P. A. Scott, S. E. Tarvares, and L. E. Peppard, "A fast multiplier forGF(2m),"IEEE J. Select. Areas Commun., vol. SAC-4, Jan. 1986.
[4] I. S. Hsu, I. S. Reed, T. K. Truong, K. Wang, C. S. Yeh, and L. J. Deutsch, "The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm,"IEEE Trans. Comput., vol. C-33, Oct. 1984.
[5] H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder,"IEEE Trans. Comput., vol. C-34, May 1985.
[6] M. Perlman and J. J. Lee, "A comparison of conventional Reed-Solomon encoders and Berlekamp's architecture," NASA Tech. Brief 3610-81-119, Jet Propulsion Lab., Pasadena, CA, July 10, 1981.
[7] C. C. Wang, "Computer simulation of finite field multiplications based on Massey-Omura's normal basis representation of field elements," private communication, 1985.

Index Terms:
VLSI architecture; finite field multipliers; dual-basis multiplier; Massey-Omura normal basis multiplier; Scott-Tavares-Peppard standard basis multiplier; NMOS technology; field effect integrated circuits; multiplying circuits; VLSI.
I.S. Hsu, T.K. Truong, L.J. Deutsch, I.S. Reed, "A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases," IEEE Transactions on Computers, vol. 37, no. 6, pp. 735-739, June 1988, doi:10.1109/12.2212
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