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Issue No.06 - June (1988 vol.37)
pp: 735-739
ABSTRACT
Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so t
INDEX TERMS
VLSI architecture; finite field multipliers; dual-basis multiplier; Massey-Omura normal basis multiplier; Scott-Tavares-Peppard standard basis multiplier; NMOS technology; field effect integrated circuits; multiplying circuits; VLSI.
CITATION
I.S. Hsu, T.K. Truong, L.J. Deutsch, I.S. Reed, "A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases", IEEE Transactions on Computers, vol.37, no. 6, pp. 735-739, June 1988, doi:10.1109/12.2212
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