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Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems
June 1988 (vol. 37 no. 6)
pp. 678-690
The effect of clocking schemes on overlapped execution performance in a digital system is described and quantified. Effects of branching, data dependencies, and resource conflicts between consecutive tasks are considered. Some problems of clocking scheme synthesis for the design of digital systems with maximum execution overlap are examined. Effects of performance of the choice of clocking sche

[1] T. Agerwala, "Microprogram optimization: A survey,"IEEE Trans. Comput., vol. C-25, pp. 962-973, Oct. 1976.
[2] A. Aho and J. Ullman,Principles of Compiler Design. Reading, MA: Addison-Wesley, 1977.
[3] M. Andrews,Principles of Firmware Engineering in Microprogram Control. Rockville, MD: Computer Science Press, 1980.
[4] G. Boulaye,Microprogramming. New York: Wiley, 1971.
[5] T. C. Chen, "Overlap and pipeline processing," inIntroduction to Computer Architecture. H. C. Stone, ed. Chicago, IL: SRA, 1975.
[6] L. W. Cotten, "Circuit implementation of high-speed pipeline systems," inProc. FJCC, AFIPS, 1965, pp. 489-504.
[7] J. Darringer, "The description, simulation and implementation of digital computer processors," Ph.D. dissertation, Dep. Elec. Eng., Carnegie-Mellon Univ., 1969.
[8] E. Davidson, "The design and control of pipelined function generators," inProc. 1971 Int. IEEE Conf. Syst., Networks, Comput., 1971, pp. 19-21.
[9] E. Davidson,et al., "Effective control for pipelined computers," inCOMPCON Dig., 1975, pp. 181-184.
[10] S. W. Director, A. C. Parker, D. P. Siewiorek, and D. E. Thomas, "A design methodology and computer aids for digital VLSI systems,"IEEE Trans. Circuits Syst., vol. CAS-28, July 1981.
[11] G. Estrin, "A methodology for design of digital systems--Supported by SARA at the age of one," inProc. Nat. Comput. Conf., NCC, 1978, pp. 313-324.
[12] P. W. Foulk and J. O'Callaghan, "AIDs--An integrated design system for digital hardware,"IEE Proc., vol. 127, Mar. 1980.
[13] T. Friedman and S. Yang, "Methods used in an automatic logic design generator (ALERT),"IEEE Trans. Comput., vol. C-18, pp. 593- 614, July 1969.
[14] E. F. Girczyc and J. P. Knight, "An ADA to standard cell hardware compiler based on graph grammers and scheduling," inProc. ICCD '84, IEEE Comput. Soc., Oct. 1984.
[15] L. Hafer, "Automated data-memory synthesis: A formal model for the specification, analysis and design of register-transfer level digital logic," Ph.D. dissertation, Dep. Elec. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, May, 1981.
[16] L. Hafer and A. Parker, "A formal method for the specification analysis, and design of register-transfer level digital logic,"IEEE Trans. Comput.-Aided Design, vol. CAD-2, Jan., 1983.
[17] C. Y. Hitchcock, "Automated synthesis of data paths," Master's thesis, Carnegie-Mellon Univ., Pittsburgh, PA, 1983.
[18] K. Irani and G. McClain, "Optimal design of central processor data paths," Tech. Rep. 58, Syst. Eng. Lab., Univ. Michigan, Ann Arbor, MI, May, 1972.
[19] H. Katzan,Computer Organization and the System/370. New York: Van Norstrand Reinhold, 1971.
[20] R. Keller, "Look-ahead processors,"Comput. Surveys, Dec., 1975.
[21] D. Knapp and A. Parker, "A data structure for VLSI synthesis and verification," Tech. Rep. Digital Integrated Syst. Center, Dep. EE-Systems, Univ. Southern California, Oct. 1983.
[22] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981.
[23] T. J. Kowalski, "The VLSI design automation assistant: A knowledge-based expert system," Ph.D. dissertation, Dep. Elec. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, Apr. 1984.
[24] G. Lawson, "Design style selector, an automated computer program implementation," Master's thesis, Dep. Elec. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, Aug. 1978.
[25] C. E. Leiserson, F. M. Rose, and J. B. Saxe, "Optimizing synchronous circuitry by retiming," inProc. Third Caltech Conf. VLSI. Rockville, MD: Computer Science Press, 1983, pp. 23-36.
[26] A. Nagle, "Automatic design of sequencers for the control of digital hardware," Ph.D. dissertation, Carnegie-Mellon Univ., Pittsburgh, PA, Oct. 1980.
[27] N. Park, "Synthesis of high-speed digital systems," Ph.D. dissertation, Dep. Elec. Eng., Univ. Southern California, Sept. 1985.
[28] N. Park and A. Parker, "Synthesis of optimal clocking schemes," inProc. 22nd Design Automat. Conf., ACM-IEEE, June 1985.
[29] A. C. Parkeret al., "The CMU design automation system," inDesign Automat. Conf. Proc., 16. ACM SIGDA, IEEE Tech. Comm. Design Automat., June, 1979.
[30] J. H. Patel and E. S. Davidson, Improving the throughput of a pipeline by insertion of delays," inProc. IEEE/ACM 3rd Annu. Symp. Comput. Architecture, 1976, pp. 159-163.
[31] D. Patterson, "STRUM: Structured microprogram development system for correct firmware,"IEEE Trans. Comput., vol. C-25, pp. 974-985, Oct. 1976.
[32] C. V. Ramamoorthy and H. F. Li, "Pipeline architecture."ACM Comput. Surveys, vol. 9, pp. 61-102, Mar. 1977.
[33] E. Snow, "Automation of module set independent register transfer level design," Ph.D. dissertation, Dep. Elec. Eng., Carnegie-Mellon University, Pittsburgh, PA, Apr. 1978.
[34] D. Thomas, "The design and analysis of an automated design style selector," Ph.D. dissertation, Dep. Elec. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, April, 1977.
[35] C. Tseng, "Automated synthesis of data paths in digital systems," Ph.D. Dep. Elec. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, Apr., 1984.
[36] G. Zimmermann, "The MIMOLA design system: A computer aided digital processor design method," inProc. 16th Design Automat. Conf., ACM SIGDA, IEEE Comput. Soc.--DATC, June 1979, pp. 53-58.

Index Terms:
clocking; maximum execution overlap; high-speed digital systems; branching; data dependencies; resource conflicts; clocks; digital systems; performance evaluation.
N. Park, A.C. Parker, "Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems," IEEE Transactions on Computers, vol. 37, no. 6, pp. 678-690, June 1988, doi:10.1109/12.2206
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