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The Cubical Ring Connected Cycles: A Fault Tolerant Parallel Computation Network
May 1988 (vol. 37 no. 5)
pp. 632-636
The cube-connected cycles network is suitable for realization in VLSI, since it satisfies the properties of degree boundedness of the nodes (=3), and regularity of layout. Another network called the cubical ring-connected cycles (CRCC) is proposed that has all the desirable features of the cube-connected cycle (CCC) and is single-cycle fault tolerant as well. The degree of each processor is les

[1] I. Koren, "A reconfigurable and fault-tolerant VLSI multiprocessor array," inProc. 8th Int. Symp. Comput. Architecture, Minneapolis, MN, May 1981, pp. 425-442.
[2] F. R. K. Chung, F. T. Leighton, and A. L. Rosenberg, "DIOGENES: A methodology for designing fault-tolerant VLSI processor arrays," inProc. 13th Fault-Tolerant Comput. Symp., June 1983, pp. 26-32.
[3] M. Sami and R. Stefanelli, "Reconfigurable architectures for VLSI implementation," inProc. Nat. Comput. Conf., May 1983, pp. 565- 577.
[4] K. S. Hedlund and L. Snyder, "Wafer-scale integration of configurable highly parallel processor," inProc. Int. Parallel Processing Conf., Aug. 1982, pp. 262-264.
[5] L. Snyder, "Introduction to the configurable, highly parallel computer,"Computer, vol. 15, pp. 47-56, Jan. 1982.
[6] M. C. Pease, "The indirect binaryn-cube microprocessor array,"IEEE Trans. Comput., pp. 458-473, May 1977.
[7] M. J. Atallah and S. R. Kosaraju, "A generalized dictionary machine for VLSI,"IEEE Trans. Comput., vol. C-34, pp. 151-155, Feb. 1985.
[8] C. S. Raghavendra and T. E. Mangir, "On the VLSI implementation of fault-tolerant architectures," inProc. 1983 Int. Conf. Comput. Design: VLSI Comput., Oct. 1983, pp. 744-747.
[9] C. S. Raghavendra, A. Avizienis, and M. Ercegovac, "Fault-tolerance in binary tree architectures," inProc. 13th Fault-Tolerant Comput. Symp., June 1983, pp. 360-364.
[10] J. W. Greene and A. El Gamal, "Configuration of VLSI arrays in the presence of defects,"J. ACM, vol. 31, no. 4, pp. 694-717, 1984.
[11] A. S. M. Hassan and V. K. Agarwal, "A modular approach to fault-tolerant binary tree architectures," inProc. 15th Fault-Tolerant Comput. Symp., June 1985, pp. 344-349.
[12] H. S. Stone, "Parallel processing with the perfect shuffle,"IEEE Trans. Comput., pp. 153-161, Feb. 1971.
[13] F. P. Preparata and J. Vuillemin, "The cube-connected cycle: A versatile network for parallel computation,"Commun. ACM, vol. 24, pp. 300-309, May 1981.
[14] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[15] C. D. Thompson, "Area-time complexity for VLSI," inProc. Eleventh Annu. ACM Symp. Theory Comput., 1979, pp. 81-88.
[16] L. Wittie, "Communication structures for large networks of microcomputers,"IEEE Trans. Comput., vol. C-30, pp. 264-273, Apr. 1981.
[17] P. Lala,Fault-tolerant and fault testable hardware design. Englewood Cliffs, NJ, Prentice-Hall, 1985.
[18] J. D. Ullman,Computational Aspects of VLSI. Rockville, MD: Computer Sci. 1984, pp. 30-34.

Index Terms:
reliability; cubical ring connected cycles; fault tolerant parallel computation network; cube-connected cycles network; VLSI; single-cycle fault tolerant; regular layout scheme; multiprocessor interconnection networks; parallel architectures; VLSI.
Citation:
P. Banerjee, "The Cubical Ring Connected Cycles: A Fault Tolerant Parallel Computation Network," IEEE Transactions on Computers, vol. 37, no. 5, pp. 632-636, May 1988, doi:10.1109/12.4617
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