This Article 
 Bibliographic References 
 Add to: 
Layer Assignment Problem for Three-Layer Routing
May 1988 (vol. 37 no. 5)
pp. 625-632
The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets so that the number of vias is minimized. The problem is often referred to as the via minimization problem. The problem is considered for three-layer routing, concentrating on one version called the constrained via minimization (CVM3) problem. It is shown that the CV

[1] A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures," inProc. Design Automat. Workshop, 1971, pp. 155-169.
[2] M. Servit, "Minimizing the number of feedthroughs in two-layer printed boards,"Digital Processes, vol. 3, pp. 177-183.
[3] K. R. Stevens and W. M. VanCleemput, "Global via elimination in generalized routing environment," inProc. 1979 ISCAS, pp. 689- 692.
[4] Y. Kajitani, "On via hole minimization of routing in a 2-layer board," inProc. IEEE 1980 Int. Conf. Circuits Comput., June 1980, pp. 295-298.
[5] F. Hadlock, "Finding a maximum cut of a planar graph in polynomial time,"SIAM Comput., vol. 4, pp. 221-225, Sept. 1975.
[6] M. J. Ciesielski and E. Kinnen, "An optimum layer assignment for routing in ICs and PCBs," inProc. 18th Design Automat. Conf., June 1981, pp. 733-737.
[7] R. W. Chen, Y. Kajitani, and S. P. Chan, "On the via minimization problem for the two-layer printed circuit board," inConf. Rec. 15th Asilomar Conf. Circuits, Syst., Comput., 1981, pp. 22-26.
[8] R. W. Chen, Y. Kajitani, and S. P. Chan, "Topological considerations of the via minimization problem for two-layer PC board," inProc. ISCAS, 1982, pp. 968-971.
[9] R. Chen, Y. Kajitani, and S. Chan, "A graph theoretic via minimization algorithm for two layer printed circuit boards,"IEEE Trans. Circuit Syst., pp. 284-299, 1983.
[10] R. Y. Pinter, "Optimal layer assignment for interconnect," inProc. ISCAS, 1982, pp. 398-401.
[11] D. T. Lee, S. J. Hong, and C. K. Wong, "Number of vias: A control parameter for global wiring of high-density chips,"IBM J. Res. Develop., vol. 25, pp. 261-271, July 1981.
[12] H. C. Du and K. C. Chang, "A new approach for layer assignment problem," Tech. Rep. TR-84-20, Dep. Comput. Sci., Univ. Minnesota, Minneapolis, MN, 1984.
[13] K. Chang and D. Du, "Efficient algorithms for the layer assignment problem,"IEEE Trans. Comput.-Aided Design, vol. CAD-6, pp. 67-78, 1987.
[14] C. P. Hsu, "Minimum via topological routing,"IEEE Trans. Comput.- Aided Design, vol. CAD-2, pp. 235-246, Oct. 1983.
[15] M. Marek-Sadowska, "An unconstraint topological via minimization,"IEEE Trans. Comput.-Aided Design, vol. CAD-3, pp. 184-190, July 1984.
[16] Y. K. Chen and M. L. Liu, "Three-layer channel routing,"IEEE Trans. Comput.-Aided Design, vol. CAD-3, pp. 156-163, Apr. 1984.
[17] S. E. Hambrusch, "Channel routing algorithms for overlap models,"IEEE Trans. Comput.-Aided Design, vol. CAD-4, pp. 23-30, Jan. 1985.
[18] N. Deo,Graph Theory with Application to Engineering and Computer Science. Englewood Cliffs, NJ: Prentice-Hall, 1974.
[19] M. R. Garey and D. S. Johnson,Computers and Intractability. San Francisco, CA: Freeman, 1979.
[20] R. Srinivasan and I. M. Patnaik, "Two algorithms for three-layer channel routing,"IEEE Trans. Comput.-Aided Design, vol. CAD- 16, pp. 264-271, Sept. 1984.
[21] M. R. Garey and D. S. Johnson, "The complexity of near-optimal graph coloring,"J. ACM, vol. 23, pp. 43-49, Jan. 1976.
[22] E. Horowitz and S. Sahni,Fundamentals of Computer Algorithms. Rockville, MD: Computer Sci. Press, 1978.
[23] K. C. Chang and H. C. Du, "Layer assignment problem for three-layer routing," TR 85-33, Dep. Comput. Sci., Univ. Minnesota, Minneapolis, MN 55455.

Index Terms:
three-layer routing; layer assignment; signal nets; constrained via minimization; CVM3; NP-complete; heuristic algorithm; circuit layout CAD; computational complexity; heuristic programming; minimisation; VLSI.
K.C. Chang, H.C. Du, "Layer Assignment Problem for Three-Layer Routing," IEEE Transactions on Computers, vol. 37, no. 5, pp. 625-632, May 1988, doi:10.1109/12.4616
Usage of this product signifies your acceptance of the Terms of Use.