Issue No.05 - May (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.4614
A method is proposed for achieving fault tolerance by introducing a redundant stage for a special-purpose fast Fourier transform (FFT) processor. A concurrent error-detection technique, called recomputing by alternate path, is used to detect errors during normal operation. Once an error is detected, a faulty butterfly can be located with log (N+5) additional cycles. The method has 100% detectio
fault-tolerant FFT processor; redundant stage; concurrent error-detection technique; recomputing by alternate path; faulty butterfly; roundoff errors; gracefully degraded reconfiguration; reliability; availability; automatic testing; digital integrated circuits; error detection; fault location; fault tolerant computing; integrated circuit testing; parallel architectures; redundancy; signal processing equipment.
Y.-H. Choi, "A Fault-Tolerant FFT Processor", IEEE Transactions on Computers, vol.37, no. 5, pp. 617-621, May 1988, doi:10.1109/12.4614