Issue No.05 - May (1988 vol.37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.4606
Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a
error location; fault tolerant FFT networks; concurrent error detection; N-point fast Fourier transform; log/sub 2/N stages; N/2 two-point butterfly modules; fault model; fault-secure results; data retry technique; roundoff errors; functional errors; physical failures; time-redundancy method; negligible hardware overhead; throughput; automatic testing; digital arithmetic; digital integrated circuits; error analysis; error detection; fast Fourier transforms; fault location; fault tolerant computing; integrated circuit testing; parallel architectures; redundancy; roundoff errors.
J.-Y. Jou, J.A. Abraham, "Fault-Tolerant FFT Networks", IEEE Transactions on Computers, vol.37, no. 5, pp. 548-561, May 1988, doi:10.1109/12.4606