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Fault-Tolerant FFT Networks
May 1988 (vol. 37 no. 5)
pp. 548-561
Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a

[1] W. T Cochran et al., "'What is the fast Fourier transform?,"IEEE Trans. Audio Electroacoust., vol. AU-15, pp. 45-55, June 1967.
[2] C. A. Glew, "The octave band vibration analyzer as a machinery defect indicator," inProc. Amer. Soc. Mechan. Eng. Int. Conf. Vibration Design Automat., Sept. 1970, Toronto, Ont., Canada, paper 71.
[3] H. C. Andrews and K. L. Caspari, "A generalized technique for analysis,"IEEE Trans. Comput., vol. C-19, pp. 16-25, Jan. 1970.
[4] J. F. Kaiser, "The digital filter and speech communications,"IEEE Trans. Audio Electroacoust., vol. AU-16, pp. 180-183, June 1968.
[5] M. J. Foster and H. T. Kung, "The design of special-purpose VLSI chaps,"IEEE Computer, pp. 26-40, Jan. 1980.
[6] H. T. Kung and C. E. Leiserson, "Algorithms for VLSI processor arrays," inIntroduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley, 1980, ch. 8.
[7] H. Stone, "Parallel Processing with the perfect shuffle,"IEEE Trans. Comput., vol. C-20, pp. 153-161, Feb. 1971.
[8] F. Preparata and J. Vuillemin, "The cube-connected cycles: A versatile network for parallel computation," inProc., 20th Annu. Symp. Foundations Comput. Sci., IEEE Comput. Soc., Oct. 1979, pp. 140- 142.
[9] C. D. Thomson, "Fourier transforms in VLSI,"IEEE Trans. Comput., vol. C-32, pp. 1047-1057, Nov. 1983.
[10] J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series,"Math Computat., vol. 19, pp. 297-301, 1965.
[11] R. C. Singleton, "An algorithm for computing the mixed radix fast Fourier transform,"IEEE Trans. Audio Electroacoust., vol. AU-17, no. 1, June 1969.
[12] I. Koren, "A reconfigurable and fault-tolerant VLSI multiprocessor array," inProc. 8th Int. Symp. Comput. Architecture, Minneapolis, MN, May 1981, pp. 425-442.
[13] S. P. Kartashev and S. I. Kartashev, "Reconfigurable fault-tolerant microcomputer network,"AFIPS Conf. Proc., Nat. Comput. Conf., Anaheim, CA, May 1983.
[14] H. T. Kuag and M. S. Lam, "Fault-tolerant VLSI systolic arrays and two-level pipelining," inProc. MIT Conf. Advance Res. VLSI, Jan. 1984, pp. 74-83.
[15] J. Jou and J. A. Abraham, "Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures,"Proc. IEEE, pp 732-741, May 1986.
[16] P. Banerjee and J. A. Abraham, "Fault-secure algorithms for multiple processor systems," inProc. 11th Int. Symp. Comput. Architecture, June 1984, pp. 279-287.
[17] Y. Chen and M. Malek, "A fault-tolerant FFT processor," inProc., 15th Annu. Int. Symp. Fault-Tolerant Comput., June 1985, pp. 266-271.
[18] R. L. Wadsack, "Fault modeling and logic simulation of CMOS and NMOS integrated circuits,"Bell Syst. Tech. J., vol. 57, pp. 1449- 1474, May-June 1978.
[19] J. Galay, Y. Crouzet, and M. Vergniault, "Physical versus logical fault models in MOS LSI circuits: Impact on their testability,"IEEE Trans. Comput., vol C-29, pp. 527-531, June 1980.
[20] P. Banerjee and J. A. Abraham, "Characterization and testing of physical failures in MOS logic circuits,"IEEE Design Test Comput., pp. 76-89, Aug. 1984.
[21] C. C. Beh, K. H. Arya, C. E. Radke, and K. E. Torku, "Do stuck fault models reflect manufacturing defects?," inProc., Int. Test Conf., Nov. 1982, pp. 35-42.
[22] H. T. Kung, "Systolic algorithms for the CMU Warp processor," inProc. 7th Int. Conf. Pattern Recognition, Montreal, P.Q., Canada, July 1981, pp. 570-577.
[23] M. J. Cormthios, K. C. Smith, and J. L. Yen, "A parallel radix-4 fast Fourier transform computer,"IEEE Trans. Comput., vol. C-24, pp. 80-92, Jan. 1975.
[24] A. Pomerleau, M. Fourier, and H. L. Buijs, "On the design of a real-time modular FFT processor,"IEEE Trans. Circuits Syst., pp. 630- 633, Oct. 1976.
[25] K. S. Anderson, "Real-time considerations for DFT algorithms," inProc. SPIE Real Time Signal Processing VI, vol. 431, San Diego, CA, Aug. 1983, pp. 230-238.
[26] A. V. Oppenheim and C. J. Weinstein, "Effects of finite register length in digital filtering and the fast Fourier transform,"Proc. IEEE, vol. 60, pp. 957-976, Aug. 1972.
[27] P. D. Welch, "A fixed-point fast Fourier transform error analysis,"IEEE Trans. Audio Electroacoust., vol. AU-17, pp. 151-157, June 1969.
[28] G. W. Snedecor and W. G. Cochran,Statistical Methods, 6th ed., Iowa State Univ., Ames IA, 1967.
[29] W. M. Gentleman and G. Sande, "Fast Fourier transform--For fun and profit," inProc. Fall Joint Comput. Conf., 1986, pp. 563-578.
[30] C. J. Weinstein, "Roundoff noise in floating point fast Fourier transform computation,"IEEE Trans. Audio Electroacoust., vol. AU-17, pp. 209-215, Sept. 1969.
[31] T. Kaneko and B. Liu, "Accumulation of round-off error in fast Fourier transforms,"J. Ass. Comput. Mach., vol. 17, pp. 637-654, Oct. 1970.
[32] R. M. Mersereau and T. C. Speake, "A unified treatment of Cooley-Tukey algorithms for the evaluation of the multidimensional DFT,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-29, pp. 1011-1018, Oct. 1981.
[33] J. Von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," inAutomata Studies, no. 34, Princeton, NJ: Princeton Univ. Press, pp. 43-99.
[34] F. P. Mathur and A. Avizienis, "Reliability analysis and architecture of a hybrid-redundant digital system: Generalized triple modular redundancy with repair,"IEEE Comput. Group Workshop Reliability Maintainability Comput. Syst., Lake of the Ozarks, MO, Oct. 1969.
[35] S. E. Butner, "Triple time redundancy, fault masking in byte-sliced systems," Tech. Rep. CSL TR 211, Comput. Syst. Lab., Dep. Elec. Eng., Stanford Univ., Standard CA, Aug. 1981.
[36] S. Laha and J. H. Patel, "Error correction in arithmetic operations using time redundancy," inProc., 13th Annu. Int. Symp. Fault-Tolerant Comput., June 1983, pp. 298-305.
[37] E. E. Swartzlander, Jr.,et al., "Sign/logarithm arithmetic for FFT implementation,"IEEE Trans. Comput., vol. C-32, pp. 526-534, June 1983.
[38] A. Rosenberg, "The Diogenes approach to testable fault-tolerant arrays of processors,"IEEE Trans. Comput., vol. C-32, pp. 902-910, Oct. 1983.

Index Terms:
error location; fault tolerant FFT networks; concurrent error detection; N-point fast Fourier transform; log/sub 2/N stages; N/2 two-point butterfly modules; fault model; fault-secure results; data retry technique; roundoff errors; functional errors; physical failures; time-redundancy method; negligible hardware overhead; throughput; automatic testing; digital arithmetic; digital integrated circuits; error analysis; error detection; fast Fourier transforms; fault location; fault tolerant computing; integrated circuit testing; parallel architectures; redundancy; roundoff errors.
J.-Y. Jou, J.A. Abraham, "Fault-Tolerant FFT Networks," IEEE Transactions on Computers, vol. 37, no. 5, pp. 548-561, May 1988, doi:10.1109/12.4606
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