This Article 
 Bibliographic References 
 Add to: 
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
April 1988 (vol. 37 no. 4)
pp. 463-468
A reconfiguration scheme is presented that is suitable for both yield and reliability enhancement of large-area VLSI implementations of binary tree architectures. The approach proposed makes use of partially global redundancy to allow clustered effects to be tolerated. The binary tree is cut a few levels above the leaves to form an upper subtree and many lower subtrees, with spare processors be

[1] A. K. Somani and V. K. Agarwal, "An efficient unsorted VLSI dictionary machine,"IEEE Trans. Comput., vol. C-34, pp. 841-852, Sept. 1985.
[2] J. Bentley and H. T. Kung, "A tree machine for searching problems," inProc. Int. Conf. Parallel Processing, 1979, pp. 257-266.
[3] C. A. Mead and L. A. Conway, "Hierarchically organized machines," inIntroduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, ch. 8.4.
[4] C. S. Raghavendra, A. Avizienis, and M. D. Ercegovac, "Faulttolerance in binary tree architectures,"IEEE Trans. Comput., vol. C- 33, pp. 568-572, June 1984.
[5] A. Rosenberg, "The Diogenes approach to testable fault-tolerant arrays of processors,"IEEE Trans. Comput., vol. C-32, pp. 902-910, Oct. 1983.
[6] A. S. M. Hassan and V. K. Agarwal, "A fault tolerant modular architecture for binary trees,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 356-361, Apr. 1986.
[7] M. B. Lowrie and W. K. Fuchs, "Reconfigurable tree architectures using subtree oriented fault tolerance,"IEEE Trans. Comput., vol. C-36, pp. 1172-1182, Oct. 1987.
[8] C. H. Stapper, "On yield, fault distributions and clustering of particles,"IBM J. Res. Develop., vol. 30, no. 3, pp. 326-338, May 1986.
[9] M. B. Ketchen, "Point defect yield model for wafer scale integration,"IEEE Circuits Devices, vol. 1, pp. 24-34, July 1985.
[10] C. H. Stapper, "Yield statistics for large area ICs," inProc. Int. Solid-State Circuits Conf., Feb. 1986, pp. 168-169.
[11] M. C. Howells, "A cluster-proof approach to yield enhancement of large area binary tree architectures," M. Eng. thesis, Dep. Elec. Eng., McGill Univ., 1987.
[12] M. Dagenais and Y. Boudreault, "Implementation of a CMOS systolic dictionary machine," inProc. Tech. Dig. Canadian Conf. VLSI, 1984, pp. 2.42-2.45.

Index Terms:
reconfiguration scheme; yield enhancement; large area binary tree architectures; reliability enhancement; VLSI; partially global redundancy; programmable switches; computer architecture; fault tolerant computing; trees (mathematics).
M.C. Howells, V.K. Agarwal, "A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures," IEEE Transactions on Computers, vol. 37, no. 4, pp. 463-468, April 1988, doi:10.1109/12.2192
Usage of this product signifies your acceptance of the Terms of Use.