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A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
April 1988 (vol. 37 no. 4)
pp. 463-468
A reconfiguration scheme is presented that is suitable for both yield and reliability enhancement of large-area VLSI implementations of binary tree architectures. The approach proposed makes use of partially global redundancy to allow clustered effects to be tolerated. The binary tree is cut a few levels above the leaves to form an upper subtree and many lower subtrees, with spare processors be

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Index Terms:
reconfiguration scheme; yield enhancement; large area binary tree architectures; reliability enhancement; VLSI; partially global redundancy; programmable switches; computer architecture; fault tolerant computing; trees (mathematics).
Citation:
M.C. Howells, V.K. Agarwal, "A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures," IEEE Transactions on Computers, vol. 37, no. 4, pp. 463-468, April 1988, doi:10.1109/12.2192
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