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Realizing Fault-Tolerant Interconnection Networks Via Chaining
April 1988 (vol. 37 no. 4)
pp. 458-462
A scheme applicable to a wide class of multistage interconnection networks to enhance their fault-tolerant capability is proposed. Multiple paths between each input-output pair of a network are created by connecting switching elements within the same stage. This scheme provides a network with alternative paths at every stage, requires a simple self-routing algorithm, and allows a network to bec

[1] C.L. Wu and T.Y. Feng,Interconnection Networks for Parallel and Distributed Processing, Computer Society Press, Los Alamitos, Calif., Order No. 574, 1984.
[2] D. H. Lawrie, "Access and alignment of data in an array processor,"IEEE Trans. Comput., vol. C-24, pp. 1145-1155, Dec. 1975.
[3] C.-L. Wu and T.-Y. Feng, "On a class of multistage interconnection networks,"IEEE Trans. Comput., vol. C-29, pp. 694-702, Aug. 1980.
[4] J. P. Shen and J. P. Hayes, "Fault tolerance of a class of connecting networks," inProc. 7th Annu. Symp. Comput. Architecture, 1980, pp. 61-71.
[5] D. S. Parker and C. S. Raghavendra, "The Gamma network: A multiprocessor interconnnection network with redundant paths," inProc. 9th Annu. Symp. Comput. Architecture, Apr. 1982, pp. 73-80.
[6] G. B. Adams III and H. J. Siegel, "The extra stage cube: A fault-tolerant interconnection network for supersystems,"IEEE Trans. Comput., vol. C-31, pp. 443-454, May 1982.
[7] J. E. Lilienkamp, D. H. Lawrie, and P.-C. Yew, "A fault tolerant interconnection network using error correcting codes," Dep. Comput. Sci. Rep. UIUCDCS-R-82-1094, Univ. Illinois Urbana-Champaign, June 1982.
[8] K. Padmanabhan, "Fault tolerance and performance improvement in multiprocessor interconnection networks," Ph.D. dissertation, Dep. Comput. Sci. Rep. UIUCDCS-R-84-1156, Univ. Illinois, Urbana-Champaign, May 1984.
[9] C. S. Raghavendra and A. Varma, "INDRA: A class of interconnection networks with redundant paths," inProc. Real-Time Syst. Symp., Dec. 1984, pp. 153-164.
[10] N.-F. Tzeng, P.-C. Yew, and C.-Q. Zhu, "A fault-tolerant scheme for multistage interconnection networks," inProc. 12th Int. Symp. Comput. Architecture, June 1985, pp. 368-375.
[11] V. P. Kumar and S. M. Reddy, "Design and analysis of fault-tolerant multistage interconnection networks with low link complexity," inProc. 12th Int. Symp. Comput. Architecture, June 1985, pp. 376- 386.
[12] D. M. Dias and J. R. Jump, "Analysis and simulation of buffered delta networks,"IEEE Trans. Comput., vol. C-30, pp. 273-282, Apr. 1981.
[13] C.-T. A. Lea, "The load-sharing banyan network,"IEEE Trans. Comput., vol. C-35, pp. 1025-1034, Dec. 1986.
[14] P. M. Lin, B. J. Leon, and T.-C. Huang, "A new algorithm for symbolic system reliability analysis,"IEEE Trans. Reliability, vol. R-25, pp. 2-15, Apr. 1976.
[15] N.-F. Tzeng, "Fault-tolerant multiprocessor interconnection networks and their fault-diagnoses," Ph.D. dissertation, Dep. Comput. Sci., Univ. Illinois, Urbana-Champaign, Aug. 1986.

Index Terms:
fault-tolerant interconnection networks; chaining; multistage interconnection networks; switching elements; self-routing algorithm; quantitative measurement; reliability improvement; fault tolerant computing; multiprocessor interconnection networks.
Citation:
N.-F. Tzeng, P.-C. Yew, C.-Q. Zhu, "Realizing Fault-Tolerant Interconnection Networks Via Chaining," IEEE Transactions on Computers, vol. 37, no. 4, pp. 458-462, April 1988, doi:10.1109/12.2191
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